Flash EEprom system

A bulk storage memory system that is connectable to a host computer system, said memory system comprising:

• an array of non-volatile floating gate memory cells arranged to store in designated blocks thereof a given amount of user data and associated overhead data, and
• a controller connectable to said computer system for controlling operation of the array, said controller including:
• an addressing circuit responsive to receipt of a mass memory storage block address from the host computer system to address a corresponding array block of user data and associated overhead data,
• a reading circuit responsive to the addressing circuit to read the associated overhead data of the addressed array block, and
• a data transfer circuit responsive to the addressing circuit and the read overhead data to execute an instruction from the host computer system to perform a designated one of reading user data from, or writing user data to, the addressed array block.

A method of operating a memory system with a host system that includes a processor, wherein the memory system includes one or more integrated circuit chips individually including an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

• providing said one or more chips and a memory controller within a card that is removably connectable to the host system, said controller being connectable to said processor for controlling operation of the memory system when the card is connected to the host system,
• operating the memory cells within the individual sectors with at least a user data portion and an overhead portion,
• detecting a predefined condition when individual sectors become unusable and linking the addresses of such unusable sectors with addresses of other sectors that are useable,
• causing the controller, in response to receipt from the processor of an address in a format designating at least one mass memory storage block, to generate an address of a non-volatile memory sector that corresponds to said at least one mass memory storage block,
• accessing a usable sector of the memory system, if the sector with the generated address is unusable, by referring to the linked address of another sector that is usable and then accessing that other sector,
• either writing data to, or reading data from, the user data portion of the accessed usable sector, and
• either writing to, or reading from, said overhead portion of the accessed usable sector, information related to either the accessed usable sector or data stored in the user data portion of said accessed useful sector.

A method of operating a memory system with a host system that includes a processor, wherein the memory system includes one or more integrated circuit chips individually including an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

• providing said one or more chips and a memory controller within a card that is removably connectable to the host system, said controller being connectable to said processor for controlling operation of the memory system when the card is connected to the host system,
• operating the memory cells within the individual sectors with at least a user data portion and an overhead portion,
• causing the controller, in response to receipt from the processor of an address in a format designating at least one mass memory storage block, to designate an address of at least one non-volatile memory sector that corresponds with said at least one mass memory storage block,
• either writing user data to, or reading from, the user data portion of said at least one non-volatile memory sector, and
• either writing to, or reading from, said overhead portion of said at least one non-volatile memory sector, overhead data related either to said at least one non-volatile memory sector or to data stored in the user data portion of said at least one non-volatile memory sector.

A memory system connectable to a host processor to enable the exchange of data therebetween, and memory system comprising:

• an array of non-volatile floating gate memory cells partitioned into a plurality of blocks of cells that individually store a given amount of user data and overhead data, wherein the memory cells are individually programmable into one of more than two distinct threshold level ranges corresponding to more than one bit of data per cell, and
• a controller connected to the array and removably connectable to the host through an electrical connector, said controller including:
• an address generator that is responsive to receipt of a mass memory storage block address from the host to address a corresponding at least one of the plurality of memory blocks, and
• a data transfer control that responds to an instruction from the host to perform a disignated one of reading user data from, or writing user data to, said at least one address block, including a data writing circuit that generates at least some of the overhead data associated with at least one of at least one addressed block or user data being written therein, and a data reading circuit that reads the overhead data from said at least one addressed block, wherein the data writing circuit programs the individual memory cells into said one of more than two distinct threshold level ranges and the data reading circuit reads one of more than two distinct threshold level ranges from the individual memory cells.

A method of operating, with a host processor, a non-volatile memory system that includes an array of non-volatile floating gate memory cells partitioned into sectors of memory cells that are erasable together as a unit, comprising:

• providing said memory array and a memory controller within a card that is removably connectable to the host processor, the controller being connectable to said host processor for controlling operation of the memory array when the card is connected to the host processor, and the memory cells within said memory array being individual programmable into one or more than two distinct threshold level ranges corresponding to more than one bit of data per cell,
• causing the controller, in response to receipt from the host processor of an address in a format designating at least one mass memory storage sector, to designate an address of at least one non-volatile memory sector that corresponds with said at least one mass memory storage block,
• either writing user data to, or reading user data from, said at least one non-volatile memory sector,
• either writing to, or reading from, said at least one non-volatile memory sector, overhead data related either to said at least one non-volatile memory sector or to user data stored in said at least one non-volatile memory sector, and
• wherein the writint of user and overhead data includes programming the individual memory cells of the array into said one of more than two distinct threshold level ranges.