US 6,148,436 A · System and method for automatic generation of gate-level descriptions from table-based descriptions for electronic design automation

Abstract

Automatic generation of gate-level descriptions from table-based descriptions within the field of electronic design automation. The gate-level and structural descriptions are used for test generation processes and some formal verification processes. For combinational table-based descriptions, ordered ternary decision diagram (OTDD) graphs are used with novel input reordering to extract prime, non-redundant cube sets that can include high level functions (e.g., XOR, XNOR, MUX). For sequential table-based descriptions, a reduced or "clock" based OTDD graph is generated from which data and clock signals are identified and characterized. Input reordering is done and a complete sequential OTDD graph is generated, followed by port separation and characterization of the sequential element. Clock and data functions are then constructed on a port-by-port basis using the prime, non-redundant cube set generation processes of the combinational logic phase. By providing an automatic generation process for the gate-level and structural descriptions, processes for verifying equivalence between the gate-level and structural descriptions and the table-based descriptions can be eliminated from the design phase.

Claims27

Dependent claims

A computer implemented method for generating a gate-level description of an integrated circuit cell, said method comprising the steps of:

a) accessing a simulation library to obtain a table-based description of said integrated circuit cell, said simulation library stored in a memory unit;
b) determining whether said table-based description describes a combinational circuit or a sequential circuit;
c) if said table-based description describes a combinational circuit, automatically generating a complete combinational ordered ternary decision diagram (OTDD) graph of said table-based description and automatically generating a gate-level description of said table-based description based on said complete combinational OTDD graph;
d) if said table-based description describes a sequential circuit, automatically generating a gate-level description of said table-based description based on a clock OTDD graph of said table-based description and also based on a complete sequential OTDD graph of said table-based description;
and
e) storing said gate-level description of said table-based description in a first library stored in said memory unit.

3 more elements

A computer system comprising a processor coupled to a bus and a memory unit coupled to said bus, said memory unit having stored therein instructions that when executed implement a method for generating a gate-level description of an integrated circuit cell, said method comprising the steps of:

a) accessing a simulation library to obtain a table-based description of said integrated circuit cell, said simulation library stored in said memory unit;
b) determining whether said table-based description describes a combinational circuit or a sequential circuit;
c) if said table-based description describes a combinational circuit, automatically generating a complete combinational ordered ternary decision diagram (OTDD) graph of said table-based description and automatically generating a gate-level description of said table-based description based on said complete combinational OTDD graph;
d) if said table-based description describes a sequential circuit, automatically generating a gate-level description of said table-based description based on a clock OTDD graph of said table-based description and also based on a complete sequential OTDD graph of said table-based description;
and
e) storing said gate-level description of said table-based description in a first library stored in said memory unit.

3 more elements

A computer implemented method for generating a gate-level description of an integrated circuit cell, said method comprising the steps of:

a) accessing a table-based description of said integrated circuit cell;
b) determining whether said table-based description describes a combinational circuit or a sequential circuit;
c) if said table-based description describes a combinational circuit, automatically generating a complete combinational ordered ternary decision diagram (OTDD) graph of said table-based description and automatically generating a gate-level description of said table-based description based on said complete combinational OTDD graph, wherein each node of said complete combinational OTDD graph represents an input and comprises:
a left edge representing a value of logical 0 for said input;
a middle edge representing a value of don't care for said input;
and a right edge representing a value of logical 1 for said input;
and
d) if said table-based description describes a sequential circuit, automatically generating a gate-level description of said table-based description based on a clock OTDD graph of said table-based description and also based on a complete sequential OTDD graph of said table-based description, wherein each node of said clock OTDD graph represents a clock input and comprises:
a left edge representing both a value of logical 0 and a signal transition from a logical 1 to a logical 0 for said clock input;
a middle edge representing both a logical 0 and a logical 1 for said clock input;
and a right edge representing both a value of logical 1 and a signal transition from a logical 0 to a logical 1 for said clock input.

8 more elements

Dependencies are inferred from the claim text.

System and method for automatic generation of gate-level descriptions from table-based descriptions for electronic design automation

Life of this patent

System and method for automatic generation of gate-level descriptions from table-based descriptions for electronic design automation

Life of this patent

Abstract

Claims27