Inserting buffers between modules to limit changes to inter-module signals during ASIC design and synthesis

A method for designing a circuit, comprising:

• dividing the circuit into a plurality of circuit modules, the plurality of circuit modules including circuit module inputs and circuit module outputs for carrying signals between the circuit modules;
• before designing the plurality of circuit modules, defining a plurality of buffer modules between the plurality of circuit modules, so that signals passing between the circuit modules pass through the plurality of buffer modules, the plurality of buffer modules including drivers of fixed drive strength coupled between upstream circuit module outputs and downstream circuit module inputs, so that changes in the designs of upstream circuit modules do not affect the drive strengths of signals feeding into downstream circuit modules;
• wherein defining the plurality of buffer modules includes defining a first buffer module as a ring surrounding a first circuit module, so that a first set of outputs from the first circuit module pass through drivers in the first buffer module, and a second set of outputs from the first circuit module pass straight through the first buffer module without passing through intervening drivers in the first buffer module;
• writing design specifications for the plurality of circuit modules and the plurality of buffer modules in a high-level design language;
• specifying constraints for the plurality of circuit modules and the plurality of buffer modules;
• synthesizing the plurality of circuit modules from the design specifications;
• wherein synthesizing the plurality of circuit modules involves converting the plurality of circuit modules from the high-level design language form into a netlist form;
• synthesizing the circuit from the plurality of circuit modules;
• verifying that the synthesized circuit meets a set of timing constraints;
• and
• making design changes if the synthesized circuit fails to meet the set of timing constraints.

A method for designing a circuit, comprising:

• dividing the circuit into a plurality of circuit modules, the circuit modules including circuit module inputs and circuit module outputs for carrying a plurality of signals between the circuit modules;
• before designing the plurality of circuit modules, defining a plurality of buffer modules as rings surrounding groups of modules from the plurality of circuit modules, so that signals passing between the groups of modules pass through the plurality of buffer modules, the plurality of buffer modules including drivers of fixed drive strength coupled between upstream circuit module outputs and downstream circuit module inputs, so that changes in the designs of upstream circuit modules do not affect the drive strengths of signals feeding into downstream circuit modules;
• wherein defining the plurality of buffer modules includes defining a first buffer module as a ring surrounding a first circuit module, so that a first set of outputs from the first circuit module pass through drivers in the first buffer module, and a second set of outputs from the first circuit module pass straight through the first buffer module without passing through intervening drivers in the first buffer module;
• writing design specifications for the plurality of circuit modules and the plurality of buffer modules in a high-level design language;
• specifying constraints for the plurality of circuit modules and the plurality of buffer modules, the constraints including output delays and output loads;
• synthesizing the plurality of circuit modules from the design specifications;
• wherein synthesizing the plurality of circuit modules involves converting the plurality of circuit modules from the high-level design language form into a netlist form;
• verifying that the plurality of synthesized circuit modules met a set of timing constraints;
• synthesizing the circuit from the plurality of circuit modules;
• verifying that the synthesized circuit meets a set of timing constraints;
• and
• if the synthesized circuit fails to meet the set of timing constraints, making design changes from the group of, re-specifying constraints for modules, re-writing design specifications for modules, and re-dividing the circuit into a plurality of modules.

A method for designing a circuit, comprising:

• dividing the circuit into a plurality of design blocks;
• dividing a design block in the plurality of design blocks into a plurality of circuit modules, the circuit modules including circuit module inputs and circuit module outputs for carrying signals between the circuit modules;
• before designing the plurality of circuit modules, defining a plurality of buffer modules between the plurality design blocks, so that signals passing between the design blocks pass through the plurality of buffer modules, the plurality of buffer modules including drivers of fixed drive strength coupled between upstream design block outputs and downstream design block inputs, so that changes in the designs of upstream circuit modules do not affect the drive strengths of signals feeding into downstream circuit modules;
• wherein defining the plurality of buffer modules includes defining a first buffer module as a ring surrounding a first circuit module, so that a first set of outputs from the first circuit module pass through drivers in the first buffer module, and a second set of outs from the first circuit module pass straight through the first buffer module without passing through intervening drivers in the first buffer module;
• writing design specifications for the plurality of circuit modules and the plurality of buffer modules in a high-level design language;
• specifying constraints for the plurality of circuit modules and the plurality of buffer modules;
• synthesizing the plurality of circuit modules from the design specifications;
• wherein synthesizing the plurality of circuit modules involves converting the plurality of circuit modules from the high-level design language form into a netlist form;
• synthesizing a design block from the plurality of circuit modules;
• verifying that the synthesized design block meets a set of timing constraints;
• making design changes if the synthesized design block fails to meet the set of timing constraints;
• synthesizing the circuit from the design block and other design blocks for the circuit;
• verifying that the synthesized circuit meets the set of timing constraints;
• and
• making design changes if the synthesized circuit fails to meet the set of timing constraints.