Bist architecture for detecting path-delay faults in a sequential circuit

A method for testing path-delay faults in a sequential test circuit convertible to one of a combinational circuit and a simplified sequential circuit comprising a combinational portion and a plurality of scan flip-flops, and using a scan-based built-in self-test architecture including a test pattern generator for generating a first test pattern, and a second test pattern, and a controller for generating a scan mode signal and a clock signal, comprising the steps of:

• (a) selecting an observation point for insertion in the test circuit at an input of one of the plural scan flip-flops by
• (i) performing path-delay fault testing for each path in a set of paths in the test circuit;
• (ii) identifying fault paths from the set of paths in which a fault is activated but not detected;
• (iii) calculating an activation frequency .phi. for each scan flip-flop based on a quantity of the faults identified as being activated but not detected and;
• (iv) selecting as observation points a predetermined number of the scan flip-flops having a highest calculated activation frequency;
• (b) setting the scan mode signal to logic zero;
• (c) applying the first test pattern to a targeted path in the test circuit at an active edge of a first clock cycle;
• (d) switching the scan mode signal to logic one before an active edge of a second clock cycle;
• (e) capturing in the scan flip-flop a circuit response of the combinational portion to the applied first test pattern and applying the second test pattern to the targeted path at the active edge of the second clock cycle;
• (f) capturing in the scan flip-flop a circuit response of the combinational portion to the applied second test pattern at an active edge of a third clock cycle while the scan mode signal remains held to logic one for two clock cycles;
• and
• (g) determining whether a signal transition is detected in the circuit response between the first and second test patterns;
• wherein said first, second and third clock cycles are consecutive clock cycles.