Pattern generating apparatus

A pattern generating apparatus comprising:

• address generating means for sequentially generating address patterns for specifying storage regions in a test memory having a plurality of storage regions with different operating speeds;
• first control means for converting said sequentially generated address patterns into a signal transfer configuration for said test memory and supplying these to said test memory to sequentially access said storage regions specified by the respective address patterns, and
• second controls means for determining a condition in which said test memory is operated with respect to the address pattern generated by said address generating means, and controlling a generation timing for said address pattern based on the determined condition,
• wherein said second control means determines said condition from the address of the data respectively stored in said plurality of storage regions and said address patterns which are sequentially generated, and
• wherein said second control means obtains a difference between a first required time required by said generating means to generate addresses and a second required time required to operate said test memory with respect to the generated address pattern, and controls said generation timing in accordance with the difference.