Back to results
US 6,148,413 AGranted
Memory under test programming and reading device
AssigneeSGS-Thomson Microelectronics S.A.
InventorsLuigi Pascucci, Marco Fontana
Life of this patent
Estimating the term…
Abstract
Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising at least two memory half-matrices, a bidirectional internal bus for the transmission of data to and from the memory half-matrices, a programming unit for each one of the at least two memory half-matrices, and a data sensing unit. The programming units are adapted to program the at least two memory half-matrices and the data sensing unit and the programming units communicate with the bidirectional internal bus to reroute onto the bus reading data and programming data of the at least two memory half-matrices.
Claims41
Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising:
- at least two memory half-matrices;
- a bidirectional internal bus for the transmission of data to and from the memory half-matrices, said bidirectional internal bus extending between respective half-matrices;
- a programming unit for each one of said at least two memory half-matrices;
- and
- a data sensing unit;
- said programming units being adapted to program said at least two memory half-matrices by transferring programming data from said bidirectional internal bus;
- and
- said data sensing unit and said programming units communicating with said bidirectional internal bus to reroute, onto said bus, reading data and programming data of said at least two memory half-matrices.
5 more elements
Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising:
- at least two memory half-matrices;
- a bidirectional internal bus for the transmission of data to and from the memory half-matrices;
- a programming unit for each one of said at least two memory half-matrices;
- and
- a data sensing unit;
- said programming units having programming lines and being adapted to program said at least two memory half-matrices;
- and
- said data sensing unit and said programming units communicating with said bidirectional internal bus to reroute, onto said bus, reading data and programming data of said at least two memory half-matrices;
- wherein each one of said programming units comprises means for generating a reference programming voltage that is adjusted to make the reference programming voltage independent of voltage drops along programming lines.
6 more elements
Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising:
- at least two memory half-matrices;
- a bidirectional internal bus for the transmission of data to and from the memory half-matrices;
- a programming unit for each one of said at least two memory half-matrices;
- and
- a data sensing unit;
- said programming units being adapted to program said at least two memory half-matrices;
- and
- said data sensing unit and said programming units communicating with said bidirectional internal bus to reroute, onto said bus, reading data and programming data of said at least two memory half-matrices;
- wherein said programming units are adapted to program said at least two memory half-matrices in parallel;
- wherein said programming units adapted to program said at least two memory half-matrices in parallel are adapted to keep a column redundancy function active, said redundancy being performed simultaneously for both of said at least two memory half-matrices, simultaneously replacing defective lines of said two half-matrices with redundancy lines.
7 more elements
A system for reading and programming a non-volatile memory device comprising:
- a memory matrix divided into a right half-matrix and a left half-matrix;
- an internal bus for the transmission of data to and from said memory matrix;
- a number n of data sensing units, each comprising a first input coupled to said left half-matrix and second input coupled to said right half-matrix, for respectively reading data from said left half-matrix and said right-half matrix, and an output coupled to said internal bus;
- and
- a number 2n of programming units, having programming lines two of said programming units being associated with each of said data sensing units, wherein a left one of said two programming units is coupled between said left half-matrix and said internal bus and a right one of said two programming units is coupled between said right half-matrix and said internal bus;
- wherein said left programming units read data from said internal bus and program said data to said left half-matrix and said right programming units read data from said internal bus and program said data to said right half-matrix;
- wherein each one of said programming units comprises means for generating a reference programming voltage that is adjusted to make the reference programming voltage independent of voltage drops along programming lines.
4 more elements
A system for reading and programming a non-volatile memory device comprising:
- a memory matrix divided into a right half-matrix and a left half-matrix,
- an internal bus for the transmission of data to and from said memory matrix,
- a number n of data sensing units, each comprising a first input coupled to said left half-matrix and second input coupled to said right half-matrix, for respectively reading data from said left half-matrix and said right-half matrix, and an output coupled to said internal bus;
- and
- a number 2n of programming units, two of said programming units being associated with each of said data sensing units, wherein a left one of said two programming units is coupled between said left half-matrix and said internal bus and a right one of said two programming units is coupled between said right half-matrix and said internal bus,
- wherein said left programming units read data from said internal bus and program said data to said left half-matrix and said right programming units read data from said internal bus and program said data to said right half-matrix,
- wherein each data sensing unit comprises,
- a sense amplifier having a first input coupled to said left half-matrix and a second input coupled to said right half-matrix, a first output and a second output,
- means for enabling and disabling said output of said data sensing unit;
- and
- output coupling means for coupling one of said first and second outputs of said sense amplifier to said enabling and disabling means,
- wherein each programming unit comprises:
- a programming device comprising a first input which receives data from said internal bus, a second input which enables and disables the programming device, a third input for receiving a reference voltage and an output for outputting said data;
- and
- direct memory access means for coupling to said memory matrix a direct memory access input from said internal bus.
12 more elements
A system, for reading and programming a non-volatile memory device comprising:
- a memory matrix divided into a right half-matrix and a left half-matrix,
- an internal bus for the transmission of data to and from said memory matrix,
- a number n of data sensing units, each comprising a first input coupled to said left half-matrix and second input coupled to said right half-matrix, for respectively reading data from said left half-matrix and said right-half matrix, and an output coupled to said internal bus;
- and
- a number 2n of programming units, two of said programming units being associated with each of said data sensing units, wherein a left one of said two programming units is coupled between said left half-matrix and said internal bus and a right one of said two programming units is coupled between said right half-matrix and said internal bus,
- wherein said left programming units read data from said internal bus and program said data to said left half-matrix and said right programming units read data from said internal bus and program said data to said right half-matrix,
- wherein each data sensing unit comprises,
- a sense amplifier having a first input coupled to said left half-matrix and a second input coupled to said right half-matrix, a first output and a second output,
- means for enabling and disabling said output of said data sensing unit;
- and
- output coupling means for coupling one of said first and second outputs of said sense amplifier to said enabling and disabling means,
- wherein said output coupling means comprises a first tristate structure coupled to said first output of said sense amplifier and having an output, a second tristate structure coupled to said second output of said sense amplifier and having an output and means for enabling the output of one of said first and second tristate structures while disabling the output of the other of said first and second tristate structures.
9 more elements
A system, for reading and programming a non-volatile memory device comprising:
- a memory matrix divided into a right half-matrix and a left half-matrix;
- an internal bus for the transmission of data to and from said memory matrix;
- a number n of data sensing units, each comprising a first input coupled to said left half-matrix and second input coupled to said right half-matrix, for respectively reading data from said left half-matrix and said right-half matrix, and an output coupled to said internal bus;
- and
- a number 2n of programming units, two of said programming units being associated with each of said data sensing units, wherein a left one of said two programming units is coupled between said left half-matrix and said internal bus and a right one of said two programming units is coupled between said right half-matrix and said internal bus;
- wherein said left programming units read data from said internal bus and program said data to said left half-matrix and said right programming units read data from said internal bus and program said data to said right half-matrix;
- wherein said programming units are adapted to maintain column redundancy, said redundancy being performed simultaneously for said left half-matrix and said right half-matrix, thereby simultaneously replacing defective lines of said left and right half-matrices with redundancy lines.
4 more elements
An apparatus for programming and reading data to and from a memory device, respectively, the apparatus comprising:
- at least two memory sub-matrices;
- a bidirectional internal bus for the transmission of data to and from the memory sub-matrices;
- and
- means for uniformly programming each of a plurality of memory cells coupled to each of a plurality of programming lines of said memory sub-matrices,
- wherein said uniform programming means programs said memory cells independent of any voltage drops along said programming lines.
2 more elements
Dependencies are inferred from the claim text.