US 6,148,398 AGranted

Setting/driving circuit for use with an integrated circuit logic unit having multi-function pins

AssigneeVIA Technologies, Inc.

InventorsWen-Ching Chang, Lin-Hung Chang, Nai-Shung Chang

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Abstract

A setting/driving circuit is provided for use in conjunction with an IC logic unit, such as a CPU having one or more multi-function pins, to provide two or more sets of data, such as a set of parameter data and a set of control data, via the same multi-function pins to the CPU. The setting/driving circuit includes a tri-state buffer and a parameter setting unit composed of two resistors and a switch, such as a jumper. When the tri-state buffer is disabled, the parameter data set by the switch is transferred to the multi-function pin of the CPU. On the other hand, when the tri-state buffer is enabled, the input data to the input port of the tri-state buffer is transferred to the multi-function pin of the CPU. The tri-state buffer can be integrated within the chip set without having to increase the total number of pins on the chip set so that the layout complexity on the motherboard can be simpler and thus easier to assemble compared to the prior art. Therefore, the proposed setting/driving circuit is easier and more cost-effective to implement on a computer motherboard than the prior art.

Claims9

Dependent claims

A setting/driving circuit for use in conjunction with an IC logic unit having at least one multi-function pin to provide a first set of data and a second set of data selectively via the multi-function pin to the IC logic unit, the IC logic unit having a preset threshold voltage to distinguish various voltage states between two values of binary logic data, with the multi-function pin being used to selectively receive the first set of data or the second set of data;

the setting/driving circuit comprising:
a buffer having an input port connected to receive the second set of data, an output port connected to the multi-function pin of the IC logic unit, and a control port used to receive a selection signal, the buffer operating in such a manner that
when the selection signal is at an enable state, the buffer is enabled to cause the voltage state at the output port thereof to take on the voltage state at the input port thereof;
and
when the selection signal is at a disable state, the buffer is disabled to cause the output port thereof to be put into a high-impedance state;
a voltage source supplying a system voltage representing a high-voltage logic state, the system voltage being higher in magnitude than the threshold voltage of the IC logic unit;
a first resistor having a first end connected to the system voltage and a second end connected to the output port of the buffer;
a second resistor having a first end connected to the ground and a second end connected to a node, the first and second resistors being set to such resistance values that allow them to divide the system voltage into a level lower than the threshold voltage of the IC logic unit to represent a low-voltage logic state;
and
a switch having a first end connected to the output port of the buffer and a second end connected to the node connected to the second resistor;
wherein
when the selection signal is switched to a disable state, the buffer is disabled to cause the output port thereof to be put into a high-impedance state, allowing the first set of data set by the switch to be transferred to the multi-function pin of the IC logic unit;
and
when the selection signal is switched to an enable state, the buffer is enabled to cause the output port thereof to take on the second set of data input to the input port thereof, allowing the second set of data to be transferred to the multi-function pin of the IC logic unit.

11 more elements

A setting/driving circuit for use in conjunction with a CPU having at least one multi-function pin to provide a set of specified parameter data or a set of control data via the multi-function pin to the CPU, the CPU being mounted in conjunction with a chip set on a computer motherboard, with the chip set including a control unit for generating the control data to the CPU and a reset signal generator for generating a selection signal to select between the transfer of the parameter data and the transfer of the control data to the CPU, the CPU having a preset threshold voltage to distinguish various voltage states between two values of binary logic data, with the multi-function pin being used to selectively receive the parameter data from the setting/driving circuit or the control data from the control unit,

the setting/driving circuit comprising:
a tri-state buffer having an input port connected to receive the control data, an output port connected to the multi-function pin of the CPU, and a control port used to receive the selection signal from the reset signal generator;
the tri-state buffer operating in such a manner that
when the selection signal is at an enable state, the tri-state buffer is enabled to cause the voltage state at the output port thereof to take on the voltage state at the input port thereof;
and
when the selection signal is at a disable state, the tri-state buffer is disabled to cause the output port thereof to be put into a high-impedance state;
a voltage source supplying a system voltage representing a high-voltage logic state, the system voltage being higher in magnitude than the threshold voltage of the CPU;
a first resistor having a first end connected to the system voltage and a second end connected to the output port of the tri-state buffer;
a second resistor having a first end connected to the ground and a second end connected to a node, the first and second resistors being set to such resistance values that allow them to divide the system voltage into a level lower than the threshold voltage of the CPU to represent a low-voltage logic state;
and
a switch having a first end connected to the output port of the tri-state buffer and a second end connected to the node which is connected to the second resistor;
wherein
when the selection signal is switched to a disable state, the tri-state buffer is disabled to cause the output port thereof to be put into a high-impedance state, allowing the parameter data set by the switch to be transferred to the multi-function pins of the CPU;
and
when the selection signal is switched to an enable state, the tri-state buffer is enabled to cause the output port thereof to take on the control data input at the input port thereof, allowing the control data from the control unit to be transferred to the multi-function pin of the CPU.

12 more elements

Dependencies are inferred from the claim text.