Shared floating-point unit in a single chip multiprocessor

A multiprocessor implemented on a single integrated circuit, comprising:

• a plurality of central processing units for executing program instructions upon integer data, each of the plurality of central processing units including an instruction decoder capable of detecting floating-point program instructions corresponding to program instructions to be executed upon floating-point operands;
• an internal bus system, for communicating data to and from the plurality of central processing units;
• and
• a single floating-point unit shared by the plurality of central processing units, coupled to each of the plurality of central processing units to receive therefrom detected floating-point instructions, and coupled to the internal bus system for receiving floating-point operands therefrom and communicating floating-point results thereto, the single floating-point unit including
• a plurality of floating-point instruction buffers, each floating-point instruction buffer receiving detected floating-point instructions from a corresponding one of the plurality of central processing units, being capable of storing a plurality of floating-point instructions and forwarding the received floating-point instructions in sequence;
• a plurality of floating-point instruction decoders, each floating-point instruction decoder receiving floating-point instructions forwarded by a corresponding one of the plurality of floating-point instruction buffers and decoding the forwarded floating-point instructions;
• a single floating-point execution unit for performing floating-point arithmetic operations upon floating-point operands received from the internal bus system according to the decoded floating-point instructions;
• a single dispatch unit connected to each of said plurality of floating-point instruction decoders and the single floating-point execution unit for controlling the single floating-point execution unit to execute a decoded floating-point instruction from a selected one of the plurality of floating-point instruction decoders.