Techniques and circuits for high yield improvements in programmable devices using redundant logic

A programmable logic device comprising:

• a plurality of logic blocks, one or more of said logic blocks capable of being enabled or disabled, wherein enabled ones of said logic blocks are powered on and disabled ones of said logic blocks are powered off;
• a plurality of routing resources, at least one of said routing resources corresponding to one of said logic blocks, wherein routing resources that correspond to said enabled ones of said logic blocks are capable of being configured to provide data paths for said enabled ones of said logic blocks and routing resources that correspond to said disabled ones of said logic blocks are capable of being configured to bypass said disabled ones of said logic blocks;
• a programming circuit coupled to said plurality of routing resources, said programming circuit capable of storing configuration data and of providing said configuration data to those of said routing resources corresponding to said enabled ones of said logic blocks said programming circuit comprises a plurality of multiplexers and a plurality of shift registers, wherein each of said multiplexers is coupled to a corresponding shift register, each of said multiplexers is capable of activating said corresponding shift register to be included in a chain of configuration shift registers or bypassing said corresponding shift register to be excluded from said chain of configuration shift registers, said programming circuit comprises N multiplexers and N shift registers, wherein an input of a first shift register is coupled an input of said programming circuit and to a first input of a first multiplexer, and an output of said first shift register is coupled to a second input of said first multiplexer, and an output of said first multiplexer is coupled to a first input of a second multiplexer and an input of a second shift register, and an output of said second shift register is coupled to a second input of said second multiplexer, and so forth until an output of said (N-1)th multiplexer is coupled to an input of an Nth shift register and a first input of an Nth multiplexer, and an output of said Nth shift register is coupled to a second input of said Nth multiplexer, wherein each of said multiplexers comprises a select input capable of receiving an enable signal having a first voltage level or a second voltage level, said first voltage level selecting a first input of said multiplexer and bypassing the corresponding shift register, and said second voltage level selecting a second input of said multiplexer and activating said corresponding shift register.

A method for programming a programmable logic device having redundant sets of logic blocks, comprising the steps of:

• (a) asserting an enable bit to a power supply enable circuit to power on at least one functional set of logic blocks;
• (b) deasserting an enable bit to a power supply enable circuit to power off if present, at least one nonfunctional set of logic blocks, thereby preventing said at least one nonfunctional set of logic blocks from drawing substantial current;
• and
• (c) configuring routing resources to provide said at least one functional set of logic blocks with input and output data paths.

A method of testing a programmable logic device having redundant sets of logic blocks comprising:

• (a) isolating a set of logic blocks by powering on said set of logic blocks and powering off all other sets of logic blocks, thereby preventing said all other sets of logic blocks from drawing substantial current;
• (b) applying a first voltage to a first end of an isolated set of logic blocks and a second voltage to a second end of said isolated set of logic blocks, said first and second voltages being different;
• and
• (c) determining whether said isolated set of logic blocks is functional or non functional.

A programmable logic device comprising:

• a plurality of logic blocks, one or more of said logic blocks capable of being enabled or disabled, wherein enabled ones of said logic blocks are powered on and disabled ones of said logic blocks are powered off thereby preventing said disabled ones of said logic blocks from drawing substantial current;
• a plurality of routing resources, at least one of said routing resources corresponding to one of said logic blocks, wherein routing resources that correspond to said enabled ones of said logic blocks are capable of being configured to provide data paths for said enabled ones of said logic blocks and routing resources that correspond to said disabled ones of said logic blocks are capable of being configured to bypass said disabled ones of said logic blocks;
• and
• a programming circuit coupled to said plurality of routing resources, said programming circuit capable of storing configuration data and of providing said configuration data to those of said routing resources corresponding to said enabled ones of said logic blocks.