Extended page mode with memory address translation using a linear shift register

Abstract

The present disclosure concerns a method and apparatus for accessing a memory device, such as a dynamic random access memory (DRAM). The DRAM has a plurality of rows, wherein each row has a plurality of DRAM paragraphs comprised of a plurality of contiguous columns. A linear shift register (LSR) translates a plurality of logical addresses to corresponding physical address locations in the DRAM. Each translated physical address is comprised of a row address and a column address. A physical address, including the row and column addresses, is accessed from the LSR. To access the DRAM paragraph at the accessed physical address, the row in the DRAM at the accessed row address location is strobed to setup and precharge the row. Following, all columns in the DRAM paragraph at the accessed physical address are strobed. After strobing the columns in a DRAM paragraph, the next physical address in the LSR, including the next row and column addresses, is accessed. The row in the DRAM at the next accessed row address is strobed to setup and precharge the row upon determining that the next row address is different than the previously accessed row address. Regardless of whether the next accessed row address is strobed or whether the previous precharge and setup is maintained, all columns in the DRAM paragraph at the accessed physical address are strobed.

Dependencies are inferred from the claim text.