US 6,148,386 A · Address generator circuity for a circular buffer

Abstract

An improved apparatus and method for providing addresses for accessing circular memory buffers is provided. An apparatus comprised of a first feedback circuit, a second feedback circuit, a beginning address register, an ending address register, and a comparator circuit. A control circuit is also provided. The beginning and ending address registers preferably include the beginning and ending addresses respectively of a circular memory buffer. The first feedback circuit is comprised of a first register, a first phase delay register, a first adder, a first displacement register, and a first multiplexer. The second feedback circuit is preferably comprised of a second register, a second phase delay register, a second adder, and a second displacement register. Preferably the control circuit based at least partially on contents of the first register, beginning address register, and ending address register, and upon a comparison by the comparison circuit between the contents of the second register and the ending address register causes either the first register or the second register contents to be supplied to an address bus.

A apparatus comprising:

a first feedback circuit comprised of:
a first register having a data input port and a data output port;
a first phase delay register having a data input port and a data output port;
a first adder having first and second data input ports and a data output port;
a first displacement register having a data output port;
wherein the data output port of the first register is connected to the data input port of the first phase delay register;
the data output port of the first phase delay register is connected to the first data input port of the first adder;
the data output port of the first adder is connected to the data input port of the first register;
the data output port of the first displacement register is connected to the second data input port of the first adder;
and
a second feedback circuit comprised of:
a second register having a data input port and a data output port;
a second phase delay register having a data input port and a data output port;
a second adder having first and second data input ports and a data output port;
a second displacement register having a data output port;
wherein the data output port of the second register is connected to the data input port of the second phase delay register;
the data output port of the second phase delay register is connected to the first data input port of the second adder;
the data output port of the second adder is connected to the data input port of the second register;
and
the data output port of the second displacement register is connected to the second data input port of the second adder;
a control circuit having an input port at least partially connected to the data output port of the first register;
and wherein the control circuit based at least partially on data at the data output port of the first register causes data at the data output port of the first register of the first feedback circuit to be supplied to an address bus during one or more first register cycles and data at the data output port of the second register of the second feedback circuit to be supplied to the address bus during one or more second register cycles and further comprising:
a beginning address register having a data output port;
an ending address register having a data output port;
wherein the data output port of the beginning address register and the data output port of the ending address register are at least partially connected to the input port of the control circuit;
and wherein the control circuit based at least partially on data at the data output port of the first register, data at the data output port of the beginning address register, and data at the data output port of the ending address register causes data at the data output port of the first register of the first feedback circuit to be supplied to an address bus during one or more first register cycles and data at the data output port of the second register of the second feedback circuit to be supplied to the address bus during one or more second register cycles.

23 more elements

Address generator circuity for a circular buffer

Life of this patent

Address generator circuity for a circular buffer

Life of this patent

Abstract

Claims12