High speed digital electronic memory having a read and write in one cycle
AssigneeUnisys Corporation
InventorKevin F. Jennings
Life of this patent
Estimating the term…
Abstract
The invention includes apparatus for controlling a high speed memory unit M that is written to on every cycle and read from on every cycle except during receipt of write commands. The apparatus includes a timing coordinator with bi-stable storage means that store and present certain signals to the memory in conjunction with clock signals so as to be immediately usable by the memory, and so that the memory can responsively output data to a user. The signals include commands R/W to Read or Write, Address signals and Data signals.
Claims13
Apparatus for controlling a high speed memory unit M to be read from and written to as initiated by clock signals CL from a clock of comparable speed, this apparatus comprising:
- timing coordinator means TC with bi-stable store means S for storing and presenting certain signals SS to said memory unit M in conjunction with said clock signals CL so as to be immediately useable by unit M, and so that unit M can responsively output data to user means;
- said signals SS being arranged to include commands R/W to Read or Write, Address signals and Data signals;
- and
- said clock signal being used as a write signal to said unit M, said unit M being written to on the second half of every clock cycle and being read from on both halves of every clock cycle except during receipt of write commands.
Dependencies are inferred from the claim text.