Single-port trace buffer architecture with overflow reduction
AssigneeAdvanced Micro Devices, Inc.
InventorRavi Jotwani
Life of this patent
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Abstract
A buffer circuit includes a buffer input, a memory, a memory controller and an upper buffer limit register. The memory is coupled to receive information from the buffer input. The memory has a single-port for accessing a plurality of storage locations for storing the information. The upper buffer limit register is for storing an upper buffer limit value. The memory controller is coupled to the memory and the upper buffer limit register. The memory controller prioritizes writes over reads when the number of storage locations of the memory storing the information is less than the upper buffer limit value. The memory controller prioritizes reads over writes when the number of storage locations storing the information is greater than the upper buffer limit value.
Claims27
A buffer circuit comprising:
- a buffer input;
- a memory coupled to receive information from the buffer input, the memory having a single-port for accessing a plurality of storage locations for storing the information;
- an upper buffer limit register for storing an upper buffer limit value;
- and
- a memory controller coupled to the memory and the upper buffer limit register, the memory controller prioritizing writes over reads when a number of the storage locations of the memory storing the information is less than the upper buffer limit value, the memory controller prioritizing reads over writes when the number of the storage locations storing the information is greater than the upper buffer limit value.
A buffer circuit comprising:
- a single-port memory system including
- a single-port memory coupled to receive input information via a buffer circuit input, the single-port memory having a plurality of storage locations;
- and
- a single-port memory controller coupled to the single-port memory;
- an upper buffer limit register coupled to the single-port memory system, the upper buffer limit register for storing an upper buffer limit value;
- wherein
- the single-port memory controller grants priority to writes over simultaneous reads while a write address generated by memory control circuitry is less than the upper buffer limit value;
- and
- the single-port memory controller grants priority to reads over simultaneous writes while the write address is greater than the upper buffer limit value.
A method of buffering information, the method comprising:
- providing an upper buffer limit value for a single-port RAM;
- storing information in the RAM regardless of whether there is a pending RAM read operation while a number of used storage locations in the RAM is less than the upper buffer limit value;
- storing information in the RAM after reading information from the RAM if there is a pending RAM read operation while the number of used storage locations in the RAM is greater than the upper buffer limit value;
- prioritizing write over read by reading information from the RAM only if there is no pending RAM store operation while the number of used storage locations in the RAM is less than the upper buffer limit value;
- and
- prioritizing read over write by reading information from the RAM regardless of whether there is a pending RAM store operation while the number of used storage locations in the RAM is greater than the upper buffer limit value.
A buffer circuit comprising:
- a single-port memory system including
- a single-port memory coupled to receive input information via a buffer circuit input, the single-port memory having a plurality of storage locations;
- and
- a single-port memory controller coupled to the single-port memory;
- an upper buffer limit register coupled to the single-port memory system, the upper buffer limit register for storing an upper buffer limit value;
- wherein
- the single-port memory controller is responsive to existence of simultaneous reads and writes and responsive to the upper buffer limit register by:
- granting priority to writes over simultaneous reads while a write address generated by memory control circuitry is less than the upper buffer limit value;
- and
- granting priority to reads over simultaneous writes while the write address is greater than the upper buffer limit value.
Dependencies are inferred from the claim text.