Apparatus and methods for increasing memory utilization
AssigneeUnited Microelectronics Corp.
InventorsJerry Hsu, Wesley Chen, Chris Hung
Life of this patent
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Abstract
A method and device for increasing memory utilization using a central processing unit with a Harvard architecture, and by putting speech data into the program memory, that is, putting both the program and the data into the same program memory, memory which is normally wasted by internal instruction is now conserved. Furthermore, no changes are required in the hardware of the central processing unit except for some minor changes to the external circuits, so the original central processing unit can be immediately used for the fabrication of prototypes and programs can be developed faster benefiting market expansion.
Claims18
A method for conserving memory in systems characterized by having a memory coupled to a central processing unit by an address bus, the method comprising the steps of:
- defining a special address space for data in the memory;
- receiving an address from the address bus;
- determining whether the address is in the special address space;
- preprocessing data from the address in the special address space by combining a part of the data from the address in the special address space with a hardware simulated op code to form a composite instruction;
- and
- sending the preprocessed data to the central processing unit.
A method for conserving memory in systems characterized by having a memory coupled to a microprocessor by an address bus, the method comprising the steps of:
- defining a special address space in an address space of the memory;
- receiving an address from the address bus;
- determining whether the address is in the special address space;
- retrieving data from the memory in accordance with the determination;
- and
- sending an instruction to the microprocessor, the instruction including the retrieved data and an op code if the address is in the special address space.
A device for increasing memory utilization in systems characterized by having a memory coupled to a central processing unit by an address bus, the device comprising:
- an address detector coupled to the address bus for detecting whether an address from the address bus is in a pre-defined address space of the memory;
- and
- a logic circuit coupled to the address detector, the memory, and the microprocessor, wherein when the address from the address bus as detected by the address detector is in the special address space, the logic circuit generates a instruction, including an op code combined with data retrieved from the memory at the address in the special address space, and provides the instruction to the microprocessor.
A device for conserving memory in systems characterized by having a memory coupled to a microprocessor by an address bus, the device comprising:
- an address detecting device for detecting whether a memory address where data requested by the microprocessor is stored is in a pre-defined special address space;
- and
- a logic circuit controlled by the address detecting device for the selective providing the requested data to the microprocessor,
- wherein when the memory address detected by the address detecting device is in the special address space, the requested data is retrieved and combined by the logic circuit with an op code to form a composite instruction that is provided to the microprocessor, and when the memory address detected by the address detecting device is not in the special address space, the requested data is retrieved and provided directly to the microprocessor.
A memory conserving device, comprising:
- a UM6610 microprocessor;
- a ROM;
- an address detecting device for detecting whether a given ROM memory address provided by the UM6610 microprocessor for retrieving data from the ROM is within a pre-defined special address space;
- and
- a logic circuit controlled by the address detecting device for retrieving the data stored in the given ROM address and selectively providing the retrieved data to the UM6610 microprocessor;
- wherein when the given ROM memory address falls within the special address space, the address detecting device signals the logic circuit to retrieve either a high byte or a low byte of the data to be combined with an internally generated RTNW op code to form a composite RTNW instruction.
A system for improving memory utilization, essentially comprising:
- an UM6610 microprocessor;
- a ROM;
- an option register for defining a special address space;
- an address detecting device for determining whether a given ROM memory address provided by the UM6610 microprocessor for retrieving data falls within the special address space;
- and
- a logic circuit for retrieving a piece of data from the ROM and combining the piece of data with a hardware generated RTNW op code to form a RTNW instruction according to a signal from the address detecting device and the determination that the given ROM address is within the special address space.
A method for increasing memory utilization in systems having a UM6610 microprocessor coupled to a memory by an address bus, the method comprising the steps of:
- defining a special address space in the memory to establish a memory area for the special treatment of RTNW instructions;
- checking an address from the address bus to determine whether the address is in the special address space or not;
- and
- providing the UM6610 microprocessor a RTNW program code, which is a combination of the retrieved data from the memory and a generated RTNW op code, according to a control signal generated when the address is in the special address space.
Dependencies are inferred from the claim text.