Multi-level non-blocking cache system with inhibiting thrashing
AssigneeSun Microsystems, Inc.
InventorsRicky C. Hetherington, Sharad Mehrotra, Ramesh Panwar
Life of this patent
Estimating the term…
Abstract
A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.
Claims15
A data cache unit associated with a processor, the data cache unit comprising:
- a first non-blocking cache receiving a data access request from a device in the processor;
- a second non-blocking cache coupled to the first non-blocking cache to service misses in the first non-blocking cache;
- a data return path coupled to the second non-blocking cache, the data return path coupling data returning from the second non-blocking cache substantially simultaneously, and in parallel, to the first non-blocking cache and to the device;
- and
- the first non-blocking cache being coupled to the data return path in a manner to provide that the returning data is synchronized with a reissue of the access request, wherein the reissued access request is generated subsequent to the cache access request that generated the miss.
A processor that executes a plurality of coded instructions comprising:
- an instruction scheduling unit receiving the coded instructions, and issuing the received coded instructions for execution;
- an instruction execution unit generating a plurality of data access requests in response to the issued coded instructions;
- a first non-blocking cache receiving the data access requests from the instruction execution unit;
- a second non-blocking cache coupled to the first non-blocking cache to service misses in the first non-blocking cache;
- a data return path coupled to the second non-blocking cache, the data return path coupling data returning from the second non-blocking cache substantially simultaneously, and in parallel, to the first non-blocking cache and to the instruction execution unit;
- and
- the returned data being coupled to the instruction execution unit in a manner to provide that the returning data is synchronized with a reissue of the cache access request, wherein the reissued access request is generated subsequent to the cache access request that generated the miss.
A non-blocking cache memory comprising:
- a first interface receiving a cache access from a lower level device including an address, wherein the applied address identifies a cache line within the cache memory that is a target of the cache access;
- means for generating a miss when the identified cache line fails to include valid data corresponding to the applied address;
- means for servicing the miss by requesting data from another memory device, wherein the servicing results in returning data to the cache;
- a second interface receiving the returning data into the cache;
- and
- means for causing the lower level device to reapply the address of the cache access to the first interface of the cache memory substantially simultaneously with the arrival of the returning data to the cache memory at the second interface of the cache memory.
Dependencies are inferred from the claim text.