Interrupt architecture for a non-uniform memory access (NUMA) data processing system

A method for handling an external interrupt in a data processing system, said method comprising:

• establishing a plurality of interrupt domains that each include at least one of a plurality of interconnected nodes, wherein each interrupt domain includes at least one processor capable of receiving an external interrupt and at least one interrupt source capable of generating an external interrupt, each of said plurality of interrupt domains having respective interrupt hardware;
• within a particular interrupt domain among said plurality of interrupt domains, receiving, at said interrupt hardware, an external interrupt generated by an interrupt source within said particular interrupt domain and first presenting said external interrupt to a processor within said particular interrupt domain by said interrupt hardware;
• invoking interrupt servicing utilizing said processor of said particular interrupt domain to which said external interrupt is first presented;
• communicating said external interrupt and inter-processor interrupts between interrupt domains utilizing a globally-accessible memory mapped register within said interrupt hardware;
• and
• servicing said external interrupt utilizing a processor within a different one of said plurality of interrupt domains than said particular interrupt domain.

A method of processing an interrupt within a data processing system including a plurality of interconnected nodes, said method comprising:

• establishing a plurality of interrupt domains that each include at least one of the plurality of interconnected nodes, wherein each interrupt domain includes at least one processor capable of receiving an interrupt and at least one device capable of generating an interrupt, and wherein devices in multiple of said plurality of interconnected nodes can generate interrupts of the same level;
• in response to presentation of an interrupt to a processor for servicing, said interrupt having a level, obtaining a list of devices capable of generating an interrupt of said level;
• polling only devices within said list located within a same interrupt domain as said processor in order to identify which device within said list generated said interrupt;
• and
• prior to presentation of said interrupt, creating and storing said list in a global memory space accessible to all of said plurality of interconnected nodes.

A data processing system, comprising:

• a plurality of interrupt domains that each include at least one of a plurality of interconnected nodes, wherein each of said plurality of interrupt domains includes at least one processor capable of receiving an interrupt and at least one device that generates interrupts, wherein devices in multiple of said plurality of interconnected nodes can generate interrupts of the same level;
• interrupt handler software stored within said data processing system and executable by said processor, wherein said interrupt handler software, in response to presentation of an interrupt having a level to said processor, obtains a list of devices capable of generating an interrupt of said level and polls only devices within said list located within a same interrupt domain as said processor in order to identify which device within said list generated said interrupt;
• and
• a global memory space accessible to all of said plurality of interconnected nodes, wherein said list is stored in said global memory space prior to presentation of said interrupt.

A program product for use by a data processing system including a plurality of interrupt domains that each include at least one of a plurality of interconnected nodes, wherein each of said plurality of interrupt domains includes at least one processor capable of receiving an interrupt and at least one device that generates interrupts, and wherein devices in multiple of said plurality of interconnected nodes can generate interrupts of the same level, said program product comprising:

• a computer usable medium;
• interrupt handler software encoded within said computer usable, medium and executable by the data processing system, wherein said interrupt handler software, in response to presentation of an interrupt having a level to said processor, obtains a list of devices capable of generating an interrupt of said level and polls only devices within said list located within a same interrupt domain as said processor in order to identify which device within said list generated said interrupt;
• and
• a configuration routine, encoded with said computer usable medium, that creates said list in global memory space accessible to all of said plurality of nodes prior to presentation of said interrupt.