Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
AssigneeAdvanced Micro Devices, Inc.
InventorsDale E. Gulick, Larry D. Hewitt
Life of this patent
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Abstract
An integrated circuit includes a central processing unit, a memory controller circuit for interfacing to system memory, and an interconnect bus controller for interfacing to an interconnect bus. The interconnect bus controller gives priority to transfer of asynchronous data during a first transfer mode and priority to transfer of isochronous data during a second transfer mode. A switch selectively couples the CPU, the memory controller circuit and the interconnect bus controller.
Claims29
An integrated circuit comprising:
- a central processing unit (CPU);
- a memory controller circuit for interfacing to a system memory;
- an interconnect bus controller for interfacing to an interconnect bus, the interconnect bus controller coupled to transfer data in asynchronous priority mode during a first part of a predetermined time period, the first part being at the beginning of the predetermined time period and wherein in asynchronous priority mode, asynchronous traffic is transferred preferentially over isochronous traffic, the interconnect bus controller being coupled to selectively switch to isochronous priority mode during another part of the predetermined time period after the asynchronous priority mode, according to an amount of isochronous data remaining to be transferred during the predetermined time period;
- and wherein
- the CPU and the memory controller circuit are coupled to the interconnect bus controller.
A computer system comprising:
- an input/output integrated circuit including a first interconnect bus controller;
- an interconnect bus coupled to the first interconnect bus controller on the input/output integrated circuit, the interconnect bus transferring data in asynchronous priority mode during a beginning part of each frame, wherein in asynchronous priority mode, asynchronous traffic is transferred preferentially over isochronous traffic, the first interconnect bus controller being coupled to transfer data in isochronous priority mode during other parts of at least some of the frames;
- and
- a processor integrated circuit including,
- a central processing unit;
- a memory controller circuit for interfacing to a system memory;
- a second interconnect bus controller coupled to the interconnect bus;
- a switching circuit selectively coupling the CPU, the memory controller circuit and the second interconnect bus controller.
A method of communicating between a first integrated circuit and an input/output integrated circuit, the first integrated circuit including a central processing unit (CPU), a memory controller circuit for interfacing to a system memory, and an interconnect bus controller interface circuit for interfacing to an interconnect bus, comprising:
- transferring information between the first integrated circuit and the input/output integrated circuit over the interconnect bus in asynchronous priority mode in which asynchronous information is preferentially transferred over isochronous information, during at least a beginning of a predetermined time period;
- and
- selectably transferring information in isochronous priority mode during another portion of the predetermined time period.
Dependencies are inferred from the claim text.