Floating point unit having a unified adder-shifter design

A storage medium having stored therein a plurality of machine readable instructions, which when executed by a program running on a processor, cause the program to effect the following:

• formally describe a floating point unit (FPU) for use in the design of in an integrated circuit (IC) that includes at least the FPU;
• and
• formally describe the FPU to include a combined adder-shifter designed to operate to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand, wherein the combined adder-shifter includes:
• (a) an adder portion designed to operate to generate a plurality of sum bits for exponent difference between the two floating point operands, favoring generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits;
• and
• (b) a shifter portion coupled to the adder portion designed to operate to shift said mantissa portion of the at least one floating point operand in accordance with the sum bits, the shifter portion designed to be capable to correspondingly shift said mantissa portion when sequential ones of the sum bits become available,
• wherein the adder portion includes a plurality of computational cells, serially coupled to each other, implementing a ripple carry scheme for lower order ones of bits employed to determine said exponent difference.

A storage medium having stored therein a plurality of machine readable instructions, which when executed by an program running on a processor, cause the program to effect the following:

• formally describe a floating point unit (FPU) for use in the design of an integrated circuit (IC) that includes at least the FPU;
• and
• formally describe the FPU to include a combined adder-shifter designed to operate to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand, wherein the combined adder-shifter includes:
• (a) an adder portion designed to operate to generate a plurality of sum bits for exponent difference between the two floating point operands, favoring generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits;
• and
• (b) a shifter portion coupled to the adder portion designed to operate to shift said mantissa portion of the at least one floating point operand in accordance with the sum bits, the shifter portion designed to be capable to correspondingly shift said mantissa portion when sequential ones of the sum bits become available,
• wherein the adder portion includes a plurality of computational cells, serially coupled to each other, implementing a carry select scheme for lower order ones of bits employed to determine said exponent difference.

An apparatus comprising:

• (a) an instruction dispatch unit that operates to dispatch floating point instructions;
• and
• (b) a floating point unit (FPU) coupled to the instruction dispatch unit that operates to execute the dispatched floating point instructions, the FPU comprising a combined adder-shifter that operates to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand, the combined adder-shifter including
• (b.1) an adder portion that operates to generate a plurality of sum bits for exponent difference between the two floating point operands of the floating point instructions, favoring generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits;
• and
• (b.2) a shifter portion coupled to the adder portion that operates to shift said mantissa portion of the at least one floating point operand of the floating point instructions in accordance with the sum bits, the shifter portion being capable to correspondingly shift said mantissa portion when sequential ones of the sum bits become available;
• wherein the adder portion includes a plurality of computational cells, serially coupled to each other, implementing a ripple carry scheme for lower order ones of bits employed to determine said exponent difference.

An apparatus comprising:

• (a) an instruction dispatch unit that operates to dispatch floating point instructions;
• and
• (b) a floating point unit (FPU) coupled to the instruction dispatch unit that operates to execute the dispatched floating point instructions, the FPU comprising a combined adder-shifter that operates to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand, the combined adder-shifter including
• (b.1) an adder portion that operates to generate a plurality of sum bits for exponent difference between the two floating point operands of the floating point instructions, favoring generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits;
• and
• (b.2) a shifter portion coupled to the adder portion that operates to shift said mantissa portion of the at least one floating point operand of the floating point instructions in accordance with the sum bits, the shifter portion being capable to correspondingly shift said mantissa portion when sequential ones of the sum bits become available;
• wherein the adder portion includes a plurality of computational cells, serially coupled to each other, implementing a carry select scheme for lower order ones of bits employed to determine said exponent difference.