Round increment in an adder circuit
AssigneeArm Limited
InventorsDavid Terrence Matheny, David Vivian Jaggar, David James Seal
Life of this patent
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AssigneeArm Limited
InventorsDavid Terrence Matheny, David Vivian Jaggar, David James Seal
Estimating the term…
A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.
Apparatus for performing a floating point addition in which a first operand is added to a second operand, said apparatus comprising:
A method of performing a floating point addition in which a first operand is added to a second operand, said apparatus comprising:
Dependencies are inferred from the claim text.