System for and method of connecting a hardware modeling element to a hardware modeling system

A system for connecting one of a plurality of hardware modeling elements to a hardware modeling system that is capable of evaluating the performance of the hardware modeling element in response to stimuli provided by the hardware modeling system, wherein each hardware modeling element of the plurality has a plurality of signal pins arranged differently from another hardware modeling element of the plurality, comprising:

• a. a connector having at least one segment for mating with a section of the hardware modeling system, such that a number of electrical signals can be bi-directionally transmitted between the connector and the hardware modeling system;
• b. a grid adapter coupled to the connector and for coupling to the hardware modeling element for providing signals to the hardware modeling element and receiving signals from the hardware modeling element, the grid adapter having a matrix of connection pads for receiving the plurality of signal pins of the hardware modeling element wherein a first connection pad is electrically coupled to a second connection pad;
• c. a generation circuit for generating and providing electrical signals to the hardware modeling element;
• and
• d. a memory circuit for storing and providing information to the hardware modeling system regarding predetermined characteristics of the hardware modeling element.

A hardware modeling system for simulating a circuit and providing signals to and measuring responses from a hardware modeling element comprising:

• a. a connector capable of being inserted to the hardware modeling system while the hardware modeling system is powered including:
• i. electrostatic charge dissipation circuitry to dissipate electrostatic charge;
• ii. a first segment including a first pin of a first length coupled to the electrostatic charge dissipation circuitry;
• iii. ground equalization circuitry to equalize ground levels of the connector, the hardware modeling system and the hardware modeling element;
• iv. a second segment including a second pin of a second length coupled to the ground equalization circuitry;
• v. power supply control circuitry to supply power from the hardware modeling system to the connector and the hardware modeling element;
• vi. a third segment including a third pin of a third length coupled to the power supply control circuitry;
• wherein the first length is longer than the second and third lengths and the second length is longer than the third length such that when the connector is inserted into the hardware modeling system, the first pin engages the hardware modeling system first, the second pin engages the hardware modeling system second and the third pin engages the hardware modeling system third;
• b. a grid adapter coupled to the connector and configured to receive the hardware modeling element for providing signals to the hardware modeling element and receiving signals from the hardware modeling element, the grid adapter comprising a matrix of connection pads arranged in concentric rectangular rings adapted for receiving one of a plurality of hardware modeling elements each having a different pin-out configuration, wherein at least one of the connection pads is electrically coupled to another one of the connection pads;
• c. a generation circuit for generating and providing electrical signals to the hardware modeling element including a voltage regulator coupled to the connector for receiving a first signal and forming a second signal, and a switch for selecting between a selective one of the first signal and the second signal for powering the hardware modeling element;
• and
• d. a memory circuit for storing and providing information to the hardware modeling system regarding predetermined characteristics of the hardware modeling element.

A method of providing electrical connections between a hardware modeler and hardware modeling elements having different footprint dimensions, the method comprising the steps of:

• a. providing a two-dimensional array of connector sockets;
• b. identifying a first plurality of the connector sockets corresponding to a first footprint dimension;
• c. connecting each of the first plurality of connector sockets to the hardware modeler;
• d. identifying a second plurality of the connector sockets corresponding to a second footprint dimension, wherein the second plurality includes a subset of the first plurality;
• and
• e. connecting each of the second plurality of connector sockets excluded by the subset to each of the first plurality of the connector sockets excluded by the subset, whereby each of the second plurality of the connector sockets are electrically coupled to the hardware modeler.

A connector capable of coupling to each of a class of electronic devices wherein each of the class of electronic devices has a different pin-out configuration, the connector configured for receiving input signals from a hardware modeling system, coupling to a selected electronic device from the class of electronic devices wherein the selected electronic device has a selected pin-out configuration, providing the input signals from the hardware modeling system to the selected electronic device, receiving a device signal from the selected electronic device and providing the device signal to the hardware modeling system for evaluating performance and response of the selected electronic device, the connector comprising:

• a. a connection pad matrix including:
• (a) a plurality of connection pads configured for coupling to the different pin-out configurations of the class of electronic devices, wherein the plurality of connection pads includes a plurality of footprint pads configured for mating with the selected pin-out configuration and receiving the device signal from the selected electronic device;
• (b) one or more segments configured for mating with the hardware modeling system, receiving the input signals and bi-directionally transmitting electrical signals between the selected electronic device and the hardware modeling system, wherein each segment is configured for receiving one or more electrical connections from the selected electronic device;
• b. a grid adaptor coupled to the connection pad matrix and configured for electrically coupling at least one of the plurality of connection pads to another of the plurality of connection pads such that each of the plurality of footprint pads is coupled to a corresponding one of the one or more segments thereby configuring the plurality of connection pads for mating with the selected pin-out configuration;
• c. a generation circuit coupled to the connection pad matrix and configured for generating and providing a power signal to the selected electronic device through the electrical connections;
• and
• d. a memory circuit coupled to the connection pad matrix and configured for storing information regarding predetermined characteristics of the selected electronic device and providing the information to the hardware modeling system.