Receive path implementation for an intermediate frequency transceiver

An automatic gain control amplifier, comprising:

• a variable gain amplifier having an input and an internal node, having a plurality of discrete selectable gain levels and having negligible phase shift variation between said discrete selectable gain levels;
• an input impedance connected between said internal node and said input;
• a feedback impedance connected between said internal node and an output of said amplifier, said plurality of discrete gain levels being dependent upon said feedback impedance and said input impedance;
• and
• a variable input compensation impedance connected between said internal node and a common mode voltaie, said variable input compensation impedance combining with said input impedance to maintain constant the impedance seen by said amplifier at said internal node;
• wherein said amplifier has a constant loop gain over all of said plurality of discrete gain levels;
• and
• wherein said input impedance is a variable input impedance and said discrete gain levels are adjusted by varying said variable input impedance.

A variable gain amplifier, comprising:

• an amplifier having an input and an internal node;
• a feedback impedance connected between said internal node and an output of said amplifier;
• an input impedance connected between said internal node and said input;
• said amplifier having a plurality of discrete gain levels dependent upon said feedback impedance and said input impedance and having negligible phase shift variation between said discrete gain levels;
• and
• a variable input compensation impedance connected between said internal node and a common mode voltage, said variable input compensation impedance combining with said input impedance to maintain constant the impedance seen by said amplifier at said internal node;
• wherein said amplifier has a constant loop gain over all of said plurality of discrete gain levels;
• and
• wherein said input impedance is a variable input impedance and said discrete gain levels are adjusted by varying said variable input impedance.

A variable gain amplifier, comprising:

• an amplifier having an input and an internal node;
• a feedback impedance connected between said internal node and an output of said amplifier;
• an input impedance connected between said internal node and said input;
• said amplifier having a plurality of discrete gain levels dependent upon said feedback impedance and said input impedance and having negligible phase shift variation between said discrete gain levels;
• and
• a variable previous-stage compensation impedance connected between said input and a common mode voltage, said variable previous-stage compensation impedance combining with said input impedance to maintain constant a load impedance seen by previous-stage circuitry;
• wherein said amplifier has a constant loop gain over all of said plurality of discrete gain levels;
• and
• wherein said input impedance is a variable input impedance and said discrete gain levels are adjusted by varying said variable input impedance.

A method for switching between discrete gain level settings in a variable gain amplifier without introducing phase shift variations, comprising:

• providing an amplifier having a plurality of discrete gain level settings defined by a ratio of a variable input impedance to a feedback impedance, said amplifier comprising:
• an input and an internal node;
• said feedback impedance connected between said internal node and an output of said amplifier;
• said variable input impedance connected between said internal node and said input, said discrete gain levels being adjusted by varying said variable input impedance;
• and
• a variable input compensation impedance connected between said internal node and a common mode voltage, said variable input compensation impedance combining with said input impedance to maintain constant the impedance seen by said amplifier at said internal node;
• adjusting said variable input impedance to select one of said plurality of discrete gain level settings;
• and
• adjusting a variable input compensation impedance to compensate for changes in said variable input impedance to keep constant a loop gain of said amplifier over all of said discrete gain level settings and to inhibit introduction of phase shift variation between said discrete gain level settings.

A method for adjusting a digital clock signal, comprising:

• receiving a digital clock signal having a first and second edge within each clock cycle;
• providing a first jitter-free output edge by passing through said first edge of said digital clock signal;
• generating a feedback signal from said digital clock signal;
• and
• triggering a second output edge based upon said feedback signal, said first jitter-free output edge and said second output edge defining an output clock cycle.

An inverting input amplifier, comprising:

• an amplifier having a finite input impedance at an operating frequency of said amplifier and having a gain that is approximately equal to a ratio of two impedances;
• and
• a shunt feedback resistor connected between an input and an output of said amplifier to adjust said finite input impedance to match a desired value;
• wherein said amplifier is an operational amplifier having a gain set by an input capacitor connected to a negative terminal of said operational amplifier and a feedback capacitor connected between an output of said operational amplifier and said negative terminal.

A method for providing matched impedance amplification with low power requirements for an intermediate frequency (IF) transceiver, comprising:

• providing an inverting amplifier with a controlled closed loop gain receiving an IF signal from a crystal filter;
• and
• connecting a shunt feedback resistor between an output and an input of said amplifier to match an input impedance of said amplifier with a load impedance desired by said crystal filter;
• wherein said providing step includes providing an operational amplifier having a gain set by an input capacitor connected to a negative terminal of said operational amplifier and a feedback capacitor connected between an output of said operational amplifier and said negative terminal.

A method for reducing aliased distortions in a discrete-time sampling receiver, comprising:

• providing a first anti-aliasing filter to receive a signal at an input frequency;
• providing a limiting amplifier connected to said first anti-aliasing filter;
• providing a second anti-aliasing filter connected to said limiting amplifier and producing an output that is to be subsequently sampled at a sampling frequency;
• estimating frequency ranges for potentially interfering distortions;
• determining rejection of distortions for said first anti-aliasing filter, said limiting amplifier circuitry, and said second anti-aliasing filter in said frequency ranges;
• adjusting parameters of at least one of said input frequency, said sampling frequency, said first anti-aliasing filter, or said second anti-aliasing filter;
• and
• repeating said estimating, said determining and said adjusting steps until said distortion rejection meets a desired level of distortion rejection.

Anti-aliasing circuitry for a discrete-time sampling receiver section of an intermediate frequency (IF) transceiver, comprising:

• a first anti-aliasing filter to receive a signal at an input frequency;
• a limiting amplifier connected to said first anti-aliasing filter;
• and
• a second anti-aliasing filter connected to said limiting amplifier and producing an output that is to be subsequently sampled at a sampling frequency;
• said input frequency, said sampling frequency, said first anti-aliasing filter, or said second anti-aliasing filter being selected so that rejection of distortion terms meets a desired level of distortion rejection at a desired after-sampling internal signal frequency.