Circuit for detecting and decoding phase encoded digital serial data
AssigneeSun Microsystems, Inc.
InventorsRobert J. Drost, Robert J. Bosnyak
Life of this patent
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Abstract
A decoder circuit for decoding phase-encoded digital data signals includes a timing circuit and a signal viewer circuit coupled to logic circuitry. The timing circuit uses an edge of a received phase-encoded digital data signal to indicate when to sample data from the received phase-encoded digital data signal in the signal viewer circuit. The logic circuitry determines the value encoded in the phase-encoded digital data signal based on the sampled data.
Claims55
A decoder apparatus for decoding a phase-encoded digital data signal comprising:
- a first delay line receiving the phase-encoded digital data signal;
- a second delay line operating at a different rate than the first delay line and receiving the phase-encoded digital data signal;
- and
- a decoder logic circuit, coupled to the first and second delay lines, configured to sample the phase-encoded digital data signal in the second delay line at times determined by the first delay line to extract a value encoded in the received phase-encoded digital data signal.
A computer system comprising:
- a memory;
- a processor, coupled to the memory, having a network interface which includes
- a decoder circuit for decoding a phase-encoded digital data signal including
- a first delay line receiving the phase-encoded digital data signal;
- a second delay line, operating at a different rate than the first delay line and receiving the phase-encoded digital data signal;
- and
- a decoder logic circuit, coupled to the first and second delay lines, configured to sample the phase-encoded digital data signal in the second delay line at times determined by the first delay line to extract a value encoded in the received phase-encoded digital data signal.
A decoder apparatus for decoding a phase-encoded digital data signal comprising:
- a timing circuit receiving the phase-encoded digital data signal;
- a signal viewer circuit receiving the phase-encoded digital data signal;
- and
- a decoder logic circuit, coupled to the timing circuit and signal viewer circuit, configured to sample the phase-encoded digital data signal in the signal viewer circuit at times determined by the timing circuit to extract a value encoded in the received phase-encoded digital data signal.
A method of decoding a phase-encoded digital data signal comprising the steps of:
- receiving the phase-encoded digital data signal;
- sampling portions of the phase-encoded digital data signal at times determined by a predetermined portion of the phase-encoded digital data signal;
- and
- extracting the value encoded in the phase-encoded digital data signal based on the sampled portions.
Dependencies are inferred from the claim text.