Synchronous semiconductor memory device capable of more reliable communication of control signal and data
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
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Abstract
In an SDRAM, an unlocked-state detection circuit detects whether synchronization between an external clock signal and an internal clock signal generated in the SDRAM according to the external clock signal is locked. When the internal clock signal is inappropriately locked, a signal output from the SDRAM to a memory controller transitions low, and the controller ignores data received and the SDRAM performs a process to ignore an input command.
Claims14
A synchronous semiconductor memory device synchronized with an external clock signal to receive an address signal and a control signal, comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns;
- a control circuit controlling an operation of said synchronous semiconductor memory device;
- a synchronizing internal signal generating circuit outputting an internal clock signal synchronized with said external clock signal;
- a synchronized-state detection circuit monitoring a condition of synchronization of said external and internal clock signals to generate a synchronized-state determination signal;
- and
- an output node for externally outputting said synchronized-state determination signal from said synchronous semiconductor memory device.
A synchronous semiconductor memory device synchronized with an external clock signal to receive an address signal and a control signal, comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns;
- a control circuit controlling an operation of said synchronous semiconductor memory device;
- a synchronizing internal signal generating circuit outputting an internal clock signal synchronized with said external clock signal;
- a synchronized-state detection circuit monitoring a condition of synchronization of said external and internal clock signals to generate a synchronized-state determination signal;
- and
- an interface circuit transmitting said synchronized-state determination signal from said synchronized-state detection circuit to the outside of said synchronous semiconductor memory device.
Dependencies are inferred from the claim text.