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US 6,147,925 AGranted
Semiconductor device allowing fast sensing with a low power supply voltage
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsShigeki Tomishima, Tsukasa Ooishi
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Abstract
In a shared sense amplifier structure, a bit line isolating gate connecting a selected memory block and a sense amplifier circuit is set to a high-resistance ON state when a sensing operation is performed, and the high-resistance ON state is held during a row selected state. A semiconductor memory device allowing fast access with a low power consumption is implemented.
Claims17
A semiconductor memory device comprising:
- a plurality of memory sub-blocks each having a plurality of memory cells arranged in rows and columns, and aligned at least in a column direction;
- a plurality of sense amplifier groups arranged for said plurality of memory sub-blocks such that memory sub-blocks adjacent each other in the column direction share a sense amplifier group, each sense amplifier group activated to sense and amplify data of a selected memory cell in a corresponding memory sub-block;
- a plurality of isolating gate groups arranged between said plurality of sense amplifier groups and said plurality of memory sub-blocks for selectively isolating corresponding sense amplifier groups from corresponding memory sub-blocks, respectively;
- and
- control circuitry responsive to a row select instruction for setting a selected isolating gate group provided for a selected memory sub-block including the selected memory cell to a high-resistance but conductive state, setting an unselected isolating gate group arranged between an unselected memory sub-block sharing the sense amplifier group with said selected memory sub-block and the shared sense amplifier group to a non-conductive state, and holding the conductive state and the non-conductive state while said selected memory sub-block is in a selected state.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of word lines arranged corresponding to said rows, respectively, each of the word lines connected to memory cells in a corresponding row;
- a plurality of bit line pairs arranged corresponding to said columns, each of the bit line pairs connected to memory cells on a corresponding column;
- a plurality of sense amplifiers provided corresponding to said plurality of bit line pairs for sensing and amplifying data of memory cells read onto the corresponding bit line pairs when active;
- a plurality of transfer gates connected between said plurality of bit line pairs and corresponding sense amplifiers;
- row select circuitry for driving a word line arranged corresponding to an addressed row to a selected state in response to a row select instruction;
- isolation control circuitry responsive to said row select instruction for setting the transfer gates to a high-resistance state at a timing after the word line arranged corresponding to said addressed row is driven to the selected state, and responsive to an instruction of completing the row selection for setting the transfer gates to a low-resistance state;
- and
- a sense control circuit responsive to said row select instruction for activating said plurality of sense amplifiers, and responsive to said instruction of completing the row selection for deactivating said plurality of sense amplifiers at a timing after said isolation control circuit sets the transfer gates to the low-resistance state,
- said row select circuitry including a circuit responsive to said instruction of completing the row selection for driving the selected word line to an unselected state at a timing after said isolation control circuitry completes setting of said low-resistance state.
7 more elements
A semiconductor memory device comprising:
- a plurality of memory sub-blocks each having a plurality of memory cells arranged in rows and columns, and aligned at least in a direction of said columns;
- a plurality of sense amplifier groups arranged for said plurality of memory sub-blocks such that memory sub-blocks adjacent each other in the column direction share a sense amplifier group, and each sense amplifier group activated to sense and amplify data of a selected memory cell in a corresponding memory sub-block;
- a plurality of isolating gate groups arranged between said plurality of sense amplifier groups and said plurality of memory sub-blocks for selectively isolating corresponding sense amplifier groups from corresponding memory sub-blocks;
- and
- control circuitry responsive to a row select instruction for setting a selected isolating gate group provided for a selected memory sub-block including the selected memory cell to a non-conductive state after transmission of the data of said selected memory cell to the corresponding sense amplifier group, and for setting an unselected isolating gate group arranged between an unselected share memory sub-block sharing the sense amplifier group with said selected memory sub-block and the shared sense amplifier group to the non-conductive state, responsive to an instruction of completing the row selection for setting said selected isolating gate group to a conductive state and then driving said shared sense amplifier group to an inactive state at a predetermined timing, and responsive to said instruction of completing the row selection for setting said unselected isolating gate group to the conductive state after inactivation of said shared sense amplifier group.
2 more elements
Dependencies are inferred from the claim text.