Arrangement of data input/output circuits for use in a semiconductor memory device

A semiconductor memory device formed on a chip comprising:

• a plurality of memory cell blocks arranged in rows and columns, wherein each memory cell block comprises a plurality of memory cells for storing data;
• a plurality of data input/output circuits divided into a first group and a second group, wherein the first group and the second group are associated with and disposed between a respective subset of the memory cell blocks, and the data input/output circuits have a data input/output pad, a data input/output buffer, and a plurality of data input/output pins;
• a plurality of address signal circuits arranged between the first group and the second group, for receiving externally applied address signals, wherein the address signal circuits have an address signal pad and an address signal buffer;
• and
• a plurality of control signal circuits arranged adjacent to the data input/output circuits of the first group and between the subset of memory cell blocks corresponding to the first group of data input/output circuits, wherein the control signal circuits have a control signal pad and a control signal buffer, and the semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first group and the second group are collectively arranged adjacent to each other.