Apparatus and method for noise reduction in DRAM
AssigneeSTMicroelectronics S.r.l.
InventorJames Brady
Life of this patent
Estimating the term…
Abstract
An apparatus (and method) is provided that reduces noise in an embedded DRAM caused by noise in the Vdd supply. A circuit switches or decouples the bit line precharge voltage supply from the memory array to reduce noise in the memory array at time of bit line sensing. In addition, another circuit is utilized to switch or decouple the memory cell plate voltage supply from the memory array to reduce noise in the memory array at the time of bit line sensing. The circuit(s) includes a switch to perform the decoupling, or alternatively, include a switch coupled in parallel with a high impedance.
Claims39
An apparatus for decreasing noise on a bit line in a memory during sensing of the bit line, the apparatus comprising:
- means for decoupling a first voltage supply from a block of memory for a predetermined time period, with at least a portion of the predetermined time period occurring during the sensing of the bit line.
An apparatus for decreasing noise on a bit line in a memory during sensing of the bit line, the apparatus comprising:
- a circuit for decoupling a first voltage supply from a block of memory for a predetermined time period, with at least a portion of the predetermined time period occurring during the sensing of the bit line.
A method for decreasing noise on a bit line in a memory during sensing of the bit line, comprising the steps of:
- precharging a plurality of bit lines in a block of memory substantially to a voltage level supplied by a first voltage supply by coupling the plurality of bit lines to the first voltage supply;
- decoupling the first voltage supply from the plurality of bit lines;
- decoupling the first voltage supply from the block of memory;
- and
- sensing the plurality of bit lines at a time when the first voltage supply is decoupled from the block of memory.
A method for decreasing noise on a bit line in a memory during sensing of the bit line, comprising the steps of:
- biasing a plurality of memory cells in the block of memory substantially to a voltage level supplied by a first voltage supply by coupling the plurality of memory cells to the first voltage supply;
- decoupling the first voltage supply from the plurality of memory cells;
- and
- sensing a bit line coupled to a one of the plurality of memory cells at a time when the first voltage supply is decoupled from the block of memory.
An apparatus for decreasing noise on a bit line in a memory during sensing of the bit line, the apparatus comprising:
- a block of memory;
- and
- means for decoupling a first voltage supply from the block of memory for a predetemined time period, with at least a portion of the predetermined time period occurring during the sensing of the bit line.
An apparatus for decreasing noise on a bit line in a memory during sensing of the bit line, the apparatus comprising:
- a block of memory;
- and
- a circuit for decoupling a first voltage supply from the block of memory for a predetermined time period, with at least a portion of the predetermined time period occurring during the sensing of the bit line.
An integrated circuit comprising:
- an apparatus for decreasing noise on a bit line in a memory during sensing of the bit line, the apparatus comprising;
- a block of memory, and
- means for decoupling a first voltage supply from the block of memory for a predetermined time period, with at least a portion of the predetermined time period occurring during the sensing of the bit line;
- and a processor.
Dependencies are inferred from the claim text.