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US 6,147,915 AGranted
Semiconductor integrated circuit
AssigneeFujitsu Limited
InventorsMakoto Yanagisawa, Kazuyuki Kanazashi, Yuji Kurita
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit includes a plurality of circuits operating in parallel in accordance with a timing signal and having an enabled state and a disabled state, a control circuit setting each of the plurality of circuits to the enable state or the disabled state in accordance with an operation mode, and a timing adjustment circuit which adjusts the timing signal in accordance with a number of circuits which are in the enabled state.
Claims13
A semiconductor integrated circuit comprising:
- a plurality of circuits operating in parallel in accordance with a timing signal and having an enabled state and a disabled state;
- a control circuit setting each of the plurality of circuits to the enable state or the disabled state in accordance with an operation mode;
- and
- a timing adjustment circuit adjusting the timing signal in accordance with a number of circuits which are in the enabled state.
1 more element
A semiconductor memory comprising:
- a plurality of blocks including memory cell arrays;
- an I/O part having output circuits which respectively correspond to the plurality of blocks, the output circuits, outputting data from the plurality of blocks in parallel in accordance with a timing signal and;
- a control circuit setting each of the output circuits to an enable state or a disabled state in accordance with an operation mode;
- and
- a timing adjustment circuit adjusting the timing signal in accordance with a number of output circuits which are in the enabled state.
2 more elements
Dependencies are inferred from the claim text.