Non-volatile semiconductor memory and method for reading data stored therein

A method of reading data from a non-volatile semiconductor memory including memory rows each having memory cells serially connected to each other, word lines commonly connected to gates of memory cell transistors within a same memory row, column lines connected to the memory cell transistors in a direction that is substantially perpendicular to the memory rows, the column lines including first column lines and second column lines located between the first column lines, and a pair of data buses selectively connected to the second column lines, the method comprising:

• supplying a bias potential to two of the first column lines which are not adjacent each other;
• selecting one of the word lines;
• selectively connecting the second column lines located next to the first column lines supplied with the bias potential, with the pair of data buses;
• and
• detecting current flowing on the pair of data buses so as to determine data stored in the memory cell transistors which are connected to the selected word line and are located between the first column lines supplied with the bias potential and the second column lines connected to the pair of data buses.

A non-volatile semiconductor memory comprising:

• a plurality of memory cell arrays each of which having a plurality of memory rows, each of the memory rows including a plurality of memory cell transistors serially connected to each other through a plurality of connection nodes;
• a plurality of word lines each of which commonly connecting a plurality of gates of the memory cell transistors of one of the memory rows;
• a plurality of column lines connected to the connection nodes in a direction substantially perpendicular to the memory rows, said column lines including first column lines and second column lines located between the first column lines;
• a plurality of first select transistors;
• a bias potential supply line connected to the first column lines through said first select transistors;
• a data bus;
• a plurality of second select transistors controlled by a memory array select signal, each of said second select transistors having a resistance lower than a resistance of each of the memory cell transistors;
• a multiplexer circuit connected to the second column lines via said second select transistors and to said data bus, said multiplexer circuit selectively connecting one of the second column lines with said data bus;
• and
• a sense amplifier connected to said data bus.

A non-volatile semiconductor memory comprising:

• a plurality of memory cell arrays each having a plurality of memory rows, each of the memory rows including a plurality of memory cell transistors serially connected to each other through a plurality of connection nodes;
• a plurality of word lines each of which commonly connects a plurality of gates of the memory cell transistors of one of the memory rows;
• a plurality of metal column lines connected to the connection nodes in a direction substantially perpendicular to the memory rows, said metal column lines including first column lines and second column lines located between the first column lines;
• a plurality of first select transistors;
• a bias potential supply line connected to the first column lines through said first select transistors;
• a plurality of second select transistors;
• a plurality of metal bit lines connected to said second column lines through said second select transistors, each of the metal bit lines having a resistance lower than a resistance of each of said metal column lines;
• a data bus;
• a multiplexer circuit connected to the metal bit lines and said data bus, said multiplexer circuit selectively connecting one of the second column lines with said data bus;
• and
• a sense amplifier connected to said data bus.