US 6,147,910 A · Parallel read and verify for floating gate memory device

Abstract

A page mode flash memory or floating gate memory device, including a page buffer based upon low current bit latches, and additional capabilities for parallel read and parallel program verify operations. The present device includes bit latch circuitry and/or method steps that facilitate such parallel operations and avoid data conflicts. Circuitry for separate read signals can serve to isolate the operations. Additionally, circuitry tied to the data verification signal can also be used. A diode type device can be used to isolate signal conditions that might indicate the cell does not need to be programmed. Bit-by-bit precharging of the bit lines can also be employed in order to save precharging power. Additionally, the large capacitance of the dataline might be used to delay discharging a particular dataline, and thereby allow a latch enabling signal to go high, thus eliminating the need for further isolation circuitry, or the like.

Claims6

Dependent claims

For an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array;

word lines coupled with corresponding rows of cells in the array, and bit latches coupled to the respective bit lines, a method providing for parallel read on the dataline, the method comprising:
setting the bit latches via application of an enabling signal;
charging up all of the bit lines;
selectively discharging and not discharging certain bit lines;
reading the bit latch;
and
locking in the bit latch and waiting for a series output.

4 more elements

Dependencies are inferred from the claim text.

Parallel read and verify for floating gate memory device

Life of this patent

Parallel read and verify for floating gate memory device

Life of this patent

Abstract

Claims6