Nonvolatile semiconductor memory device
AssigneeNEC Corporation
InventorRyosuke Fujio
Life of this patent
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Abstract
It is an object of the invention to provide an EEPROM, in which the third positive potential for erase verify is supplied from a negative potential generating circuit for supplying a negative or ground potential to a word line. The EEPROM is composed of a P potential supply circuit for respectively supplying a potential to sources of P channel transistors in invertors, which are respectively connected with word lines, a N potential supply circuit for respectively supplying a potential to sources of N channel transistors in the invertors, a read/write decision circuit for deciding whether the EEPROM operates in a read or write mode, and an erase decision circuit for deciding whether the EEPROM operates in an erase mode or not.
Claims6
A nonvolatile semiconductor memory device (an electrically erasable and programmable read only memory, EEPROM, comprising:
- invertors respectively connected with word lines,
- a P potential supply circuit for supplying a potential to sources of P channel transistors in said invertors,
- a N potential supply circuit for supplying a potential to sources of N channel transistors in said invertors,
- a read/write decision circuit for deciding whether said EEPROM operates in a write or read mode, and
- an erase decision circuit for deciding whether said EEPROM operates in an erase mode or not,
- wherein said P potential supply circuit outputs one of a first positive potential, a second positive potential and a ground potential;
- and said N potential supply circuit outputs one of a third positive potential, a ground potential and a negative potential in accordance with output signals of said read/write decision circuit and said erase decision circuit.
An EEPROM comprising:
- invertors respectively connected with word lines,
- a P potential supply circuit for supplying a potential to sources of P channel transistors in said invertors,
- plural N potential supply circuits, which are respectively provided for said invertors and supply potentials to sources of N channel transistors in said invertors,
- a read/write decision circuit for deciding whether said EEPROM operates in a write or read mode,
- a erase decision circuit for deciding whether said EEPROM operates in an erase mode or not,
- wherein said P potential supply circuit outputs one of a first positive potential, a second positive potential and a ground potential;
- and said N potential supply circuits output one of a third positive potential, a ground potential and a negative potential in accordance with output signals of said read/write decision circuit and said erase decision circuit, and
- a counter, which counts numbers assigned to said word lines responding to said third positive potential serving as a trigger signal and drives said plural N potential supply circuits based on an output of said counter.
Dependencies are inferred from the claim text.