Biasing scheme to reduce stress on non-selected cells during read
AssigneeAdvanced Micro Devices, Inc.
InventorsTimothy Thurgate, Ravi Sunkavalli
Life of this patent
Estimating the term…
Abstract
A method of reading a flash memory (EEPROM) device by applying zero volts to all bitlines and source terminals in the flash memory device. A negative voltage (V.sub.D) is applied to all the substrate and all wordlines in the flash memory device. The negative voltage (-V.sub.D) is applied to the bitline to which the drain of the cell being read is attached and applying a positive voltage (V.sub.G) minus the voltage V.sub.D to the wordline to which the gate of the cell being read is attached.
Claims4
A method of reading a flash memory Electrically-Erasable Programmable Read-Only Memory (EEPROM) that includes a multitude of field effect transistor memory cells each having a source, drain, floating gate, control gate and a substrate, the method comprising:
- (a) applying zero voltage to all bitlines in the flash memory device;
- (b) applying a negative voltage (-V.sub.D) to all wordlines in the flash memory device;
- (c) applying zero volts to each source of the multitude of memory cells in the flash memory device;
- (d) applying the negative voltage (-V.sub.D) to each substrate of the multitude of memory cells in the flash memory device;
- (e) applying the negative voltage (-V.sub.D) to a bitline to which the drain of the cell to be read is attached;
- and
- (f) applying a positive voltage (V.sub.G) minus the voltage (V.sub.D) to a wordline to which the gate of the cell to be read is attached.
Dependencies are inferred from the claim text.