High storage capacity non-volatile memory

#The present invention relates to non-volatile memories. More particularly, the invention concerns a high storage capacity non-volatile memory.

#The market demand for non-volatile semiconductor memory devices with higher and higher storage capacity is known. The manufacturers are therefore constantly coping with the task of finding solutions suitable for achieving the desired storage capacity at the same time keeping the production costs reasonable.

#A promising technique provides for storing in each single non-volatile memory cell more than just one bit of information. This technique is also known as multiple-level programming and sensing. While in conventional, bilevel non-volatile memory devices each memory cell can take only two distinct programming states, i.e., written and erased, in multiple-level devices each memory cell can take more than two programming states, for example four, corresponding to two bits of information.

#The features of the present invention will be made apparent by the following detailed description of two particular embodiments thereof, illustrated by way of example in the annexed drawings.

#FIG. 1 is a schematic block diagram of a memory device according to the present invention.

#FIG. 2 is a more detailed view of a memory block of the device shown in FIG. 1, in a first embodiment of the invention.

#FIG. 1 shows a schematic block diagram of a memory device according to the present invention. The memory device comprises a matrix of memory cells 1. Conventionally, the memory matrix 1 is a bidimensional array of memory cells (the latter are not shown, since they are conventional), that are arranged at the intersection of rows (word lines) WL and columns (bit lines) BL.

#The memory matrix includes eight memory blocks B0-B7. Each memory block B0-B7 is associated to two respective data output lines (O0,O1), (O2,O3) . . . (O14,O15) of the memory device.

#A row address decoding circuit 2 receives a subset A0-A11 (row address signals) of a set A0-A21 of address signals. The row address decoding circuit 2 decodes the digital code carried by the row address signals A0-A11 and consequently activates one out of 4096 word lines WL. The detailed structure of the row address decoding circuit 2 will not be described, being considered well known to the skilled technicians.