Semiconductor memory operating electrically and optically, retaining information without power supply

A semiconductor memory having a unit cell, said unit cell comprising a stacked structure including:

• a first semiconductor layer of a first conductivity type;
• a second semiconductor layer of an intrinsic type disposed on the first semiconductor layer so that conduction and valance band edges smoothly continue to those of the first semiconductor layer respectively;
• a third semiconductor layer of a second conductivity type opposite to said first conductivity type, being held in an electrically floating state, disposed on the second semiconductor layer so that conduction and valance band edges smoothly increase from those of the second semiconductor layer respectively so as to have a first potential maximum of band diagram in the third semiconductor layer;
• a fourth semiconductor layer of said intrinsic type adjoining said third semiconductor layer so that conduction and valance band edges smoothly continue to those of the third semiconductor layer respectively;
• a fifth semiconductor layer of said second conductivity type adjoining said fourth semiconductor layer so that conduction and valance band edges smoothly increase from those of the fourth semiconductor layer respectively so as to have a second potential maximum of band diagram in the fifth semiconductor layer;
• a sixth semiconductor layer of said intrinsic type disposed on the fifth semiconductor layer so that conduction and valance band edges smoothly decrease from those of the fifth semiconductor layer respectively;
• and
• a seventh semiconductor layer of said first conductivity type disposed on the sixth semiconductor layer so that conduction and valance band edges smoothly continue to those of the sixth semiconductor layer respectively;
• wherein a voltage is applied between said first and seventh semiconductor layers so that a potential barrier height defined by the first and second potential maxima varies with a polarity and a level of said voltage, configured such that majority carriers surmount the first and second potential maxima.

A semiconductor memory having a multi-layer structure, said structure comprising, in a stacked manner in turn:

• a first semiconductor layer of a first conductivity type;
• a second semiconductor layer of an intrinsic type disposed on the first semiconductor layer so that conduction and valance band edges smoothly continue to those of the first semiconductor layer respectively;
• a third semiconductor layer of a second conductivity type opposite to said first conductivity type, being held in an electrically floating state, disposed on the second semiconductor layer so that conduction and valance band edges smoothly increase from those of the second semiconductor layer respectively so as to have a first potential maximum of band diagram in the third semiconductor layer;
• a fourth semiconductor layer of said intrinsic type disposed on the third semiconductor layer so that conduction and valance band edges smoothly decreased from those of the third semiconductor layer respectively;
• a fifth semiconductor layer of said first conductivity type disposed on the fourth semiconductor layer so that conduction and valance band edges smoothly continue to those of the fourth semiconductor layer respectively;
• a sixth semiconductor layer of said intrinsic type disposed on the fifth semiconductor layer so that conduction and valance band edges smoothly continue to those of the fifth semiconductor layer respectively;
• a seventh semiconductor layer of said second conductivity type, being held in the electrically floating state, disposed on the sixth semiconductor layer so that conduction and valance band edges smoothly increase from those of the sixth semiconductor layer respectively so as to have a second potential maximum of band diagram in the seventh semiconductor layer;
• an eighth semiconductor layer of said intrinsic type disposed on the seventh semiconductor layer so that conduction and valance band edges smoothly decrease from those of the seventh semiconductor layer respectively;
• and
• a ninth semiconductor layer of said first conductivity type disposed on the eighth semiconductor layer so that conduction and valance band edges smoothly continue to those of the eight semiconductor layer respectively,
• wherein a first voltage is applied between said ninth and fifth semiconductor layer so that a first potential barrier height defined by the second potential maximum is varied with a polarity and a level of said first voltage and a second voltage is applied between said first and fifth semiconductor layers so that a second potential barrier height defined by the first potential maximum is varied with the polarity and the level of said second voltage, configured such that majority carriers surmount the first and second potential maximum, respectively.