Semiconductor static random access memory device with low power consumption in a write operation

A semiconductor memory comprising:

• a plurality of memory cells located in the form of a matrix, said memory cells comprising a plurality of bit lines;
• a plurality of ground lines connected to the memory cells and parallel to the bit lines;
• floating means for bringing a selected ground line of the plurality of ground lines into an electrically floating condition so as to make the selected ground line a pseudo-ground line;
• and
• connecting means for electrically connecting said pseudo-ground line to a selected bit line of said plurality of bit lines to be written with "0", when data is to be written to said selected memory cell,
• wherein said pseudo-ground line is shared by a pair of memory cells adjacent to each other in a row direction.

A semiconductor memory, comprising:

• a plurality of memory cells located in the form of a matrix, said memory cells comprising a plurality of bit lines;
• a plurality of ground lines connected to the memory cells and parallel to the bit lines;
• floating means for bringing a selected ground line of the plurality of ground lines into an electrically floating condition so as to make the selected ground line a pseudo-ground line;
• and
• connecting means for electrically connecting said pseudo-ground line to a selected bit line of said plurality of bit lines to be written with "0" when data is to be written to said selected memory cell,
• wherein said selected bit line is shared by a pair of memory cells adjacent to each other in a row direction.

A semiconductor memory comprising:

• a plurality of memory cells comprising a plurality of bit lines;
• a plurality of ground lines connected to the memory cells;
• a floating unit for bringing a selected ground line of the plurality of ground lines into an electrically floating condition so as to make the selected ground line a pseudo-ground line;
• and
• a connector for electrically connecting said pseudo-ground line to a selected bit line of said plurality of bit lines to be written with a predetermined value, when data is to be written to said selected memory cell,
• wherein said selected bit line is shared by a pair of memory cells.

A semiconductor memory comprising:

• a plurality of memory cells comprising a plurality of bit lines;
• a plurality of ground lines connected to the memory cells;
• a floating unit for bringing a selected ground line of the plurality of ground lines into an electrically floating condition so as to make the selected ground line a pseudo-ground line;
• and
• a connector for electrically connecting said pseudo-ground line to a selected bit line of said plurality of bit lines to be written with a predetermined value, when data is to be written to said selected memory cell, and
• wherein said pseudo-ground line is shared by a pair of memory cells.

A semiconductor static random access memory (SRAM) device comprising:

• a memory cell array comprising a number of memory cells arranged in rows and in columns;
• a plurality of pairs of bit lines connected to said memory cells, each pair of said plurality of bit lines being shared among said memory cells arranged in a column, and said bit lines being parallel to each other;
• a plurality of pseudo-ground lines connected to said memory cells, each of said pseudo-ground lines being shared among said memory cells arranged in a column, said pseudo-ground lines being parallel to each other and being parallel to said bit lines;
• floating means for electrically disconnecting a selected one of said pseudo-ground lines from a physical ground line;
• and
• connecting means for electrically equalizing said selected pseudo-ground line to the bit line written with "0" of a selected pair among said bit lines.

A semiconductor SRAM device comprising:

• a plurality of units each of which comprises:
• a memory cell array including a plurality of memory cells arranged in rows and in columns;
• a plurality of pairs of bit lines connected to said memory cells, each pair of bit lines being shared among said memory cells arranged in a column, and said bit lines being parallel to each other;
• a plurality of pseudo-ground lines connected to said memory cells, each of said pseudo-ground lines being shared among said memory cells arranged in a column, said pseudo-ground lines being parallel to each other and being parallel to said bit lines;
• floating means for electrically disconnecting a selected one of said pseudo-ground lines from a physical ground line;
• and
• connecting means for electrically equalizing said selected pseudo-ground line to the bit line written with "0" of a selected pair among said bit lines, and
• wherein a plurality of pairs of bit lines and a plurality of pseudo-ground lines are simultaneously selected.