Programmable read only memory with high speed differential sensing at low operating voltage

A read only memory (ROM) circuit having high-speed differential sensing at low operating voltage level, said ROM circuit comprising:

• a plurality of word lines, each of said plurality of word lines providing access to a group of data memory cells;
• a plurality of bitlines, said plurality of bitlines disposed approximately perpendicular to said word lines, said bitlines providing access to individual data memory cells within said group of data memory cell;
• and
• a plurality of programmable memory cells, each of said plurality of programmable memory cells having a gate, a first electrode, and a second electrode, said first electrode and said second electrode insulatively coupled to said gate, said gate connected to said word line in which it resides, said first electrode of each of said plurality of programmable memory cells coupled to said bitline in which it resides, wherein each of said plurality of programmable memory cells is configurable to a plurality of logic states by coupling or decoupling said second electrode of each of said plurality of programmable memory cells from ground at a location immediately adjacent to said second electrode.

In a read only memory (ROM) circuit, a method of storing a binary digit in a non-volatile memory cell transistor having a gate insulatively coupled to a first electrode and a second electrode, said method comprising the steps of:

• coupling said gate of said memory cell transistor to a word line;
• coupling said first electrode of said memory cell transistor to a bitline;
• and
• coupling said second electrode of said memory cell transistor to ground if said memory cell is desired to represent a logic 0 or decoupling said memory cell transistor from ground immediately adjacent to said second electrode if said memory cell is desired to represent a logic 1, said memory cell transistor consequently providing approximately equal capacitance to said bitline for both logic condition 0 and logic condition 1.

In a read only memory (ROM) circuit, a method of reading binary data from data memory cells at high speed and at low operating voltage level, said method comprising the steps of:

• precharging a bitline with a high logic level of voltage from a precharge circuit;
• discharging the high logic level of voltage from said bitline to ground via a memory cell coupled to said bitline if said memory cell has a logic 0 state;
• maintaining the high logic level of voltage at said bitline by not discharging said bitline to ground via a memory cell coupled to said bitline at a first electrode and uncoupled from ground at a location immediately adjacent at a second electrode if said memory cell has a logic 1 state, said logic 0 and said logic 1 state of said memory cells having approximately equal capacitance;
• and
• sensing a voltage level of said bitline after said voltage level has stabilized.

A read only memory (ROM) circuit having high-speed differential sensing at low operating voltage level, said ROM circuit comprising:

• a plurality of word lines, each of said plurality of word lines providing access to a group of data memory cells;
• a plurality of bitlines, said plurality of bitlines disposed approximately perpendicular to said word lines, said bitlines providing access to individual data memory cells within said group of data memory cell;
• a plurality of programmable memory cells, each of said plurality of programmable memory cells having a gate, said gate coupled to said word line in which it resides, each of said plurality of programmable memory cells coupled to said bitline in which it resides, each of said plurality of programmable memory cells coupled to ground to represent a logic level of 1 and decoupled from ground to represent a logic level of 0;
• and
• a dummy circuit for providing a capacitive load equivalent to and in-phase of the capacitive load of one of said plurality of bitlines to which it will be compared, said dummy circuit selectively coupled to said plurality of word lines.

In a read only memory (ROM) circuit, a method of reading binary data from data memory cells at high speed and at low operating voltage level, said method comprising the steps of:

• discharging all non-desired bitlines to ground, thereby reducing coupling capacitance noise between adjacent bitlines;
• precharging a bitline with a high logic level of voltage from a precharge circuit;
• discharging the high logic level of voltage from said bitline to ground via a memory cell coupled to said bitline if said memory cell has a logic 0 state;
• maintaining the high logic level of voltage at said bitline by not discharging bitline to ground via said memory cell if said memory cell has a logic 1 state, said logic 0 and said logic 1 state of said memory cells having approximately equal capacitance;
• and
• sensing a voltage level of said bitline after said voltage level has stabilized.