Optional on chip power supply bypass capacitor
AssigneeE. R. W.
InventorsEugene Robert Worley, Richard Arthur Mann
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes main power busses located on the next to the top most level of metal and a top level of metal separated from the main power busses by a thin dielectric. The top most level metal is connected to one of the power buses either through bond wires or through contacts. This structure provides a distributed bypass capacitance between the power buses thus stabilizing the power bus voltage within the integrated circuit. Furthermore, this capacitance structure can be optional and can be made with one or two masking steps.
Claims3
A semiconductor integrated circuit comprising:
- a semiconductor substrate;
- circuits formed on said substrate;
- power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits;
- an insulating layer formed on said substrate over said power and ground rails;
- a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor;
- means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails;
- said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to a bond pad connected to at least one of said power rails or to at least one of said ground rails.
A semiconductor integrated circuit comprising:
- a semiconductor substrate;
- circuits formed on said substrate;
- power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits;
- an insulating layer formed on said substrate over said power and ground rails;
- a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor;
- means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails;
- said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to a bond pad located on a package which connects to a power pin or to a ground pin.
A semiconductor integrated circuit comprising:
- a semiconductor substrate connected to a package floor metal plate;
- circuits formed on said substrate;
- power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits;
- an insulating layer formed on said substrate over said power and ground rails;
- a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor;
- means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails;
- said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to said package floor metal plate.
Dependencies are inferred from the claim text.