US 6,147,668 AGranted

Digital display unit of a computer system having an improved method and apparatus for sampling analog display signals

AssigneeGenesis Microchip Inc.

InventorAlexander Julian Eglit

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Abstract

A digital display unit for minimizing the display artifacts which may be caused by aliasing of high frequency distortions present in wide bandwidth analog display signals. The minimization is achieved by modulating a sampling clock signal by different phase delay amounts for successive lines or frame. Due to such modulation, the analog display signal is sampled at different sampling points in different frames for the same pixel position. As digital display screens are typically designed to respond slowly to differing scanning intensities and as the human eye generally averages different color intensities at the same point, a low-pass filter effect may be in place with respect to the samples taken at the same pixel position. Display artifacts are minimized due to the sampling at different sampling points and the low-pass filter effect.

Claims15

Dependent claims

A method of displaying a plurality of image frames on a display screen of a digital display unit, wherein said plurality of image frames are encoded in an analog display signal, wherein said analog display signal includes an analog display data and corresponding synchronization signals, wherein each of a plurality of portions of said analog display data encodes a pixel data element value included in a plurality of pixel data element values, said plurality of pixel data element values defining a corresponding image frame, said method comprising the steps of:

(a) receiving said analog display signal in said digital display unit;
(b) generating an intermediate clock signal synchronized with said synchronization signals;
(c) sampling said analog display data using a sampling clock signal to generate a plurality of sampled data values;
(d) displaying images on said display screen based on said sampled data values generated in step (c);
(e) generating said sampling clock signal by modulating said intermediate clock signal by a different phase delay amount for successive image frames,
(f) maintaining a phase delay control register to specify said phase delay amount by which said intermediate clock is to be modulated;
(g) generating a randomization sequence table including a plurality of randomization values;
(h) selecting one of said plurality of randomization values at the beginning of reception of each of said plurality of frames;
and
(i) storing said randomization value selected in step (h) into said phase delay control register such that said selected randomization value specifies said phase delay by which said intermediate clock is to be modified,
wherein the modulation by a different phase delay amount in step (e) causes said analog display data to be sampled at different sampling points for the same pixel position in said successive image frames.

8 more elements

A circuit for generating a sampling clock signal for an analog to digital converter (ADC) in a digital display unit, said ADC being used to sample a display signal, wherein said display signal includes an analog display data and corresponding synchronization signals, wherein each of a plurality of portions of said analog display data encodes a pixel data element value included in a plurality of pixel data element values, said plurality of pixel data element values defining a corresponding image frame, said circuit comprising:

a clock generator circuit for generating an intermediate clock signal synchronized with said synchronization signals, wherein said intermediate clock signal specifies a specific sampling point at which said ADC samples each of said plurality of portions of said analog display data to recover a corresponding pixel data element value;
a modulation circuit for modulating said intermediate clock signal by a different phase delay amount for successive image frames of said analog display signal, such that said analog display data is sampled at different sampling points for the same pixel position in said successive image frames, wherein at least some of said different sampling points are different from said specific sampling point specified by said intermediate clock signal synchronized with said synchronization signals, wherein said modulation circuit comprises:
a delay determination circuit for determining an amount of phase delay by which said intermediate clock is to be modulated, wherein said delay determination block comprises a programmable register for storing a number indicative of said amount of phase delay, and wherein said delay determination block receives a new number from a memory in response to a beginning of new image frame being received in said analog display signal, said delay determination block storing said new number in said programmable register such that said amount of phase delay is varied for each of said successive frames;
and
an adjustable delay block for modulating said intermediate clock signal by said amount of phase delay.

2 more elements

A computer system, comprising:

a central processing unit (CPU) coupled to a bus;
a random access memory coupled to said bus;
a graphics controller circuit receiving a plurality of pixel data element values from said CPU, said graphics controller circuit generating an analog display signal including an analog display data and corresponding synchronization signals, wherein each of a plurality of portions of said analog display data encodes a pixel data element value included in said plurality of pixel data element values, said plurality of pixel data element values defining a corresponding image frame, wherein a plurality of image frames are encoded in said analog display signal;
a digital display unit coupled to said graphics controller circuit, said digital display unit for displaying said plurality of image frames, said digital display unit comprising:
a digital display screen;
a clock generator circuit for generating an intermediate clock signal synchronized with said synchronization signals;
a modulation circuit for generating a sampling clock signal by modulating said intermediate clock signal by different phase delay amounts for successive image frames, wherein said modulation circuit comprises:
a delay determination circuit for determining an amount of phase delay by which said intermediate clock is to be modulated, wherein said delay determination block comprises a programmable register for storing a number indicative of said amount of phase delay, and wherein said delay determination block receives a new number from a memory in response to a beginning of new image frame being received in said analog display signal, said delay determination block storing said new number in said programmable register such that said amount of phase delay is varied for each of said successive frames;
and
an adjustable delay block for modulating said intermediate clock signal by said amount of phase delay,
an analog to digital converter (ADC) coupled to said modulation circuit, said ADC receiving said sampling clock and sampling said analog display data to generate a plurality of pixel data elements, wherein modulation by different phase delay amounts causes said ADC to sample said analog display data at different sampling points for the same pixel position in said successive image frames;
and
an interface for generating display signals on said digital display screen based on said plurality of pixel data elements.

10 more elements

Dependencies are inferred from the claim text.