Phase/frequency detector with time-delayed inputs in a charge pump based phase locked loop and a method for enhancing the phase locked loop gain

A phase locked loop (PLL) circuit with time-delayed phase/frequency detector (PFD) input signals for generating PFD gain, the circuit comprising:

• a first divider for receiving digital input signals with reference frequency and period T, for dividing the reference frequency by a value R, and creating a plurality of time-delayed reference output signals in each period T, each said output signal with a different time delay;
• a plurality of phase/frequency detectors, each having a first and a second output, a reference input, and a feedback input, and receiving on the reference input one of the plurality of time-delayed reference output signals from the first divider;
• a first OR means for receiving the first output signals from the plurality of said PDFs;
• a second OR means for receiving the second output signals from the plurality of said PDFs;
• a charge pump having two inputs for receiving signals output from the first and second OR means;
• a loop filter connected to an output of the charge pump;
• a voltage-controlled oscillator (VCO) connected to an output of the loop filter for providing an output signal with VCO frequency;
• and
• a second divider, connected to an output of the VCO, for dividing the VCO frequency by a value M, and creating a plurality of time-delayed feedback output signals in each period T, each said output signal with a different time delay, wherein
• each said PFD receiving, on the feedback input, one of the plurality of time-delayed feedback output signals from the second divider, and
• the delayed reference signal and the delayed feedback signal at the inputs of each said PFD having the same time delay.

A method for enhancing the gain of a phase locked loop (PLL) circuit having a first divider, a phase/frequency detector (PFD) having a plurality of input pairs, each said input pair having a reference input and a feedback input, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a second divider, the method comprising the steps of:

• receiving digital input signals with reference frequency and period T in the first divider, and creating an output signal by dividing the reference frequency by a value R;
• providing a plurality of time-delayed PFD reference input signals in each period T, by a plurality of input signal reference delay means connected in a series between the first divider and the PFD, each said input signal with a different time delay;
• dividing the VCO frequency by a value M in the second divider;
• and
• providing a plurality of time-delayed PFD feedback input signals in each period T, by a plurality of feedback signal delay devices connected in a series, each said input signal with a different time delay, wherein the delayed reference signal and the delayed feedback signal at each said PFD input pair have substantially the same time delay.

A method for enhancing the gain of a phase locked loop (PLL) circuit having a first divider, a plurality of phase/frequency detectors (PFDs), each having a first and a second output, a reference input, and a feedback input, a charge pump having a first and a second input, two OR means, a loop filter, a voltage-controlled oscillator (VCO), and a second divider, the method comprising the steps of:

• receiving digital input signals with reference frequency and period T in the first divider, dividing the reference frequency by a value R, and creating a plurality of time-delayed reference output signals in each period T, each said output signal with a different time delay;
• receiving on each said PFD reference input one of the plurality of time-delayed reference output signals from the first divider;
• or-ing the first output signals from the plurality of said PDFs and supplying a first charge pump input;
• or-ing the second output signals from the plurality of said PDFs and supplying a second charge pump input;
• dividing the VCO frequency by a value M in the second divider;
• creating a plurality of time-delayed feedback output signals in each period T in the second divider, each said output signal with a different time delay;
• and
• supplying each said PFD feedback input with one of the plurality of time-delayed feedback output signals, wherein the time-delayed reference output signal and the time-delayed feedback output signal at the inputs of each said PFD having the same time delay.

A method for enhancing the gain of a phase locked loop (PLL) circuit with a phase/frequency detector (PFD) having a plurality of input pairs, the method comprising the steps of:

• receiving digital input signals with reference frequency and period T;
• creating a plurality of time-delayed reference output signals from the digital input signals in each period T;
• receiving on each PFD reference input one of the plurality of time-delayed reference output signals;
• creating a plurality of time-delayed feedback output signals from the loop output signals in each period T;
• and
• supplying each PFD feedback input with one of the plurality of time-delayed feedback output signals, wherein the time-delayed reference output signal and the time-delayed feedback output signal at each said PFD input pair having the same time delay.

A method for enhancing the gain of a phase locked loop (PLL) circuit having a plurality of phase/frequency detectors (PFDs), comprising the steps of:

• receiving digital input signals with reference frequency and period T;
• creating a plurality of time-delayed reference output signals from the digital input signals in each period T;
• receiving on each PFD reference input one of the plurality of time-delayed reference output signals;
• or-ing output signals from the plurality of said PDFs and supplying a charge pump, loop filter and voltage-controlled oscillator (VCO) connected in a series;
• creating a plurality of time-delayed feedback output signals in each period T from the VCO output signal;
• and
• supplying each PFD feedback input with one of the plurality of time-delayed feedback output signals, wherein the time-delayed reference output signal and the time-delayed feedback output signal at the inputs of each said PFD having the same time delay.