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US 6,147,551 AGranted
Switched capacitor circuit and method for reducing sampling noise
AssigneeMotorola, Inc.
InventorMerit Y. Hong
Life of this patent
Estimating the term…
Abstract
A switched capacitor circuit (60) reduces sampling noise by oversampling an input signal in space domain. The switched capacitor circuit (60) includes four sampling capacitors (72, 74, 76, 78) serially coupled together via five integrating switches (71, 73, 75, 77, 79). Each clock cycle of the oversampling process has a sampling phase and an integrating phase. In the sampling phase, the integrating switches (71, 73, 75, 77, 79) are nonconductive and the sampling capacitors (72, 74, 76, 78) sample the input signal through eight sampling switches (81, 82, 83, 84, 85, 86, 87, 88). In the integrating phase, the charge stored in the sampling capacitors (72, 74, 76, 78) is transferred to an integrator (90).
Claims21
A method for reducing sampling noise, comprising:
- charging a first plurality of capacitors by applying a first voltage across each capacitor in the first plurality of capacitors having a value that is a difference between a first input signal and a reference voltage;
- isolating the first plurality of capacitors from the first input signal;
- charging a second plurality of capacitors by applying a second voltage across each capacitor in the second plurality of capacitors having a value that is a difference between a second input signal and the reference voltage;
- isolating the second plurality of capacitors from the second input signal;
- and
- transferring the charge stored in the first plurality of capacitors to one input of an integrator and the charge stored in the second plurality of capacitors to another input of the integrator.
3 more elements
A switched capacitor circuit, comprising:
- a first plurality of integrating switches, each integrating switch in the first plurality of integrating switches having a control electrode coupled for receiving a first clock signal, a first current conducting electrode, and a second current conducting electrode;
- a first plurality of sampling capacitors serially coupled with the first plurality of integrating switches to form a first arrangement of alternating integrating switches and sampling capacitors, each sampling capacitor in the first arrangement having a first electrode coupled to the second current conducting electrode of a preceding integrating switch, and a second electrode coupled to the first current conducting electrode of a subsequent integrating switch, wherein the first current conducting electrode of a first integrating switch in the first arrangement is coupled for receiving a first reference voltage;
- a first plurality of sampling switches, each sampling switch in the first plurality of sampling switches having a control electrode coupled for receiving a second clock signal, a first current conducting electrode coupled to the first electrode of a corresponding sampling capacitor in the first arrangement, and a second current conducting electrode coupled for receiving a first input signal;
- a second plurality of sampling switches, each sampling switch in the second plurality of sampling switches having a control electrode coupled for receiving the second clock signal, a first current conducting electrode coupled to the second electrode of a corresponding sampling capacitor in the first arrangement, and a second current conducting electrode coupled for receiving a first reference signal;
- and
- an integrator having a first input coupled to the second current conducting electrode of a last integrating switch in the first arrangement, and a first output coupled for transmitting a first output signal.
3 more elements
A switched capacitor circuit, comprising:
- a first sampling capacitor having a first electrode and a second electrode;
- a second sampling capacitor having a first electrode and a second electrode;
- a third sampling capacitor having a first electrode and a second electrode;
- a first sampling switch having a control electrode coupled for receiving a first clock signal, a first current conducting electrode coupled to the first electrode of the first sampling capacitor, and a second current conducting electrode;
- a second sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the second electrode of the first sampling capacitor, and a second current conducting electrode;
- a third sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the first electrode of the second sampling capacitor, and a second current conducting electrode;
- a fourth sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the second electrode of the second sampling capacitor, and a second current conducting electrode coupled to the second current conducting electrode of the second sampling switch;
- a fifth sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the first electrode of the third sampling capacitor, and a second current conducting electrode coupled to the second current conducting electrodes of the third sampling switch;
- a sixth sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the second electrode of the third sampling capacitor, and a second current conducting electrode coupled to the second current conducting electrode of the second sampling switch;
- a first integrating switch having a control electrode coupled for receiving a second clock signal, a first current conducting electrode, and a second current conducting electrode coupled to the first electrode of the first sampling capacitor;
- a second integrating switch having a control electrode coupled for receiving the second clock signal, a first current conducting electrode coupled to the second electrode of the first sampling capacitor, and a second current conducting electrode coupled to the first electrode of the second sampling capacitor;
- a third integrating switch having a control electrode coupled for receiving the second clock signal, a first current conducting electrode coupled to the second electrode of the second sampling capacitor, and a second current conducting electrode coupled to the first electrode of the third sampling capacitor;
- and
- an integrator having a first input coupled to the first current conducting electrode of the first integrating switch, a first output, and a second output.
11 more elements
A wireless communication device, comprising:
- a first plurality of integrating switches, each integrating switch in the first plurality of integrating switches having a control electrode coupled for receiving a first clock signal, a first current conducting electrode, and a second current conducting electrode;
- a first plurality of sampling capacitors serially coupled with the first plurality of integrating switches to form a first arrangement of alternating integrating switches and sampling capacitors, each sampling capacitor in the first arrangement having a first electrode coupled to the second current conducting electrode of a preceding integrating switch, and a second electrode coupled to the first current conducting electrode of a subsequent integrating switch, wherein the first current conducting electrode of a first integrating switch in the first arrangement is coupled for receiving a first reference voltage;
- a first plurality of sampling switches, each sampling switch in the first plurality of sampling switches having a control electrode coupled for receiving a second clock signal, a first current conducting electrode coupled to the first electrode of a corresponding sampling capacitor in the first arrangement, and a second current conducting electrode coupled for receiving a first input signal;
- a second plurality of sampling switches, each sampling switch in the second plurality of sampling switches having a control electrode coupled for receiving the second clock signal, a first current conducting electrode coupled to the second electrode of a corresponding sampling capacitor in the first arrangement, and a second current conducting electrode coupled for receiving a first reference signal;
- and
- an integrator having a first input coupled to the second current conducting electrode of a last integrating switch in the first arrangement, and a first output coupled for transmitting a first output signal.
3 more elements
A wireless communication device, comprising:
- a first sampling capacitor having a first electrode and a second electrode;
- a second sampling capacitor having a first electrode and a second electrode;
- a third sampling capacitor having a first electrode and a second electrode;
- a first sampling switch having a control electrode coupled for receiving a first clock signal, a first current conducting electrode coupled to the first electrode of the first sampling capacitor, and a second current conducting electrode;
- a second sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the second electrode of the first sampling capacitor, and a second current conducting electrode;
- a third sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the first electrode of the second sampling capacitor, and a second current conducting electrode;
- a fourth sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the second electrode of the second sampling capacitor, and a second current conducting electrode coupled to the second current conducting electrode of the second sampling switch;
- a fifth sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the first electrode of the third sampling capacitor, and a second current conducting electrode coupled to the second current conducting electrode of the third sampling switch;
- a sixth sampling switch having a control electrode coupled for receiving the first clock signal, a first current conducting electrode coupled to the second electrode of the third sampling capacitor, and a second current conducting electrode coupled to the second current conducting electrode of the second sampling switch;
- a first integrating switch having a control electrode coupled for receiving a second clock signal, a first current conducting electrode, and a second current conducting electrode coupled to the first electrode of the first sampling capacitor;
- a second integrating switch having a control electrode coupled for receiving the second clock signal, a first current conducting electrode coupled to the second electrode of the first sampling capacitor, and a second current conducting electrode coupled to the first electrode of the second sampling capacitor;
- a third integrating switch having a control electrode coupled for receiving the second clock signal, a first current conducting electrode coupled to the second electrode of the second sampling capacitor, and a second current conducting electrode coupled to the first electrode of the third sampling capacitor;
- and
- an integrator having a first input coupled to the first current conducting electrode of the first integrating switch, a first output, and a second output.
11 more elements
Dependencies are inferred from the claim text.