US 6,147,544 A · Data transfer circuit transferring complementary data signals

Abstract

First and second pairs of input/output lines transfer mutually complementary data signals respectively. First and second selection circuits select a signal transfer line having the same potential as that of a signal transfer line not precedently selected from two precedently selected signal transfer lines among first to third signal transfer lines and the signal transfer line not precedently selected and connect first ends thereof to the first pair of input/output lines respectively while connecting second ends thereof to the second pair of input/output lines respectively. Thus, no precharging may be performed for equalizing the potentials of the two signal transfer lines selected for present data transfer with each other, and hence reduction of a data transfer rate can be prevented.

Claims17

Dependent claims

A data transfer circuit comprising:

first and second nodes receiving mutually complementary data signals;
third and fourth nodes transmitting said mutually complementary data signals;
first to third signal transfer lines;
and
a selection circuit disposed to select a signal transfer line having the same potential as that of a precedently non-selected signal transfer line from two precedently selected signal transfer lines and said precedently non-selected signal transfer line among said first to third signal transfer lines and connect first ends thereof to said first and second nodes respectively while connecting second ends thereof to said third and fourth nodes respectively.

2 more elements

A data transfer circuit comprising:

first and second nodes receiving mutually complementary data signals;
third and fourth nodes transmitting said mutually complementary data signals;
first to third signal transfer lines;
a selection circuit disposed to select said second signal transfer line and a precedently non-selected one of said first and third signal transfer lines a precedently non-selected and connect first ends thereof to said first and second nodes respectively while connecting second ends thereof to said third and fourth nodes respectively;
and
a precharge circuit disposed to precharge a non-selected one of said first and third signal selection lines at the same potential as that of said second signal transfer line.

3 more elements

A data transfer circuit comprising:

first and second nodes receiving mutually complementary data signals;
third and fourth nodes transmitting said mutually complementary data signals;
first to fourth signal transfer lines;
a first selection circuit disposed to alternately select said first and second signal transfer lines and said third and fourth signal transfer lines in response to a clock signal and connect first ends of said selected two signal transfer lines to said first and second nodes respectively;
a second selection circuit disposed to connect second ends of said two signal transfer lines selected by said first selection circuit to said third and fourth nodes respectively;
a first connection circuit disposed to connect said first signal transfer line and said third signal transfer line with each other when said third signal transfer line has precedently been at a logical low level and said first signal transfer line presently transfers a signal of a logical low level;
a second connection circuit disposed to connect said first signal transfer line and said third signal transfer line with each other when said first signal transfer line has precedently been at a logical low level and said third signal transfer line presently transfers a signal of a logical low level;
a third connection circuit disposed to connect said first signal transfer line and said fourth signal transfer line with each other when said fourth signal transfer line has precedently been at a logical low level and said first signal transfer line presently transfers a signal of a logical low level;
a fourth connection circuit disposed to connect said first signal transfer line and said fourth signal transfer line with each other when said first signal transfer line has precedently been at a logical low level and said fourth signal transfer line presently transfers a signal of a logical low level;
a fifth connection circuit disposed to connect said second signal transfer line and said third signal transfer line with each other when said third signal transfer line has precedently been at a logical low level and said second signal transfer line presently transfers a signal of a logical low level;
a sixth connection circuit disposed to connect said second signal transfer line and said third signal transfer line with each other when said second signal transfer line has precedently been at a logical low level and said third signal transfer line presently transfers a signal of a logical low level;
a seventh connection circuit disposed to connect said second signal transfer line and said fourth signal transfer line with each other when said fourth signal transfer line has precedently been at a logical low level and said second signal transfer line presently transfers a signal of a logical low level;
an eighth connection circuit disposed to connect said second signal transfer line and said fourth signal transfer line with each other when said second signal transfer line has precedently been at a logical low level and said fourth signal transfer line presently transfers a signal of a logical low level;
a first precharge circuit disposed to precharge said first signal transfer line at a logical high level after a lapse of a prescribed time from connection by said second or fourth connection circuit;
a second precharge circuit disposed to precharge said second signal transfer line at a logical high level after a lapse of a prescribed time from connection by said sixth or eighth connection circuit;
a third precharge circuit disposed to precharge said third signal transfer line at a logical high level after a lapse of a prescribed time from connection by said first or fifth connection circuit;
and
a fourth precharge circuit disposed to precharge said fourth signal transfer line at a logical high level after a lapse of a prescribed time from connection by said third or seventh connection circuit.

15 more elements

Dependencies are inferred from the claim text.

Data transfer circuit transferring complementary data signals

Life of this patent

Data transfer circuit transferring complementary data signals

Life of this patent

Abstract

Claims17