Reset circuit for flipflop
AssigneeNEC Corporation
InventorKou Sasaki
Life of this patent
Estimating the term…
Abstract
In order to prevent the value of a flipflop from being indefinite during a period from a power-on time to the time a first clock signal is inputted, a reset circuit for a flipflop is configured to supply a clock to a clock input terminal of each of flipflops at the power-on time, so that an output of each flipflop never becomes indefinite. For example, in the case that an input/output of tristate buffers coinected in common to the same bus are controlled by a corresponding number of flipflops, respectively, a pass-through current caused for an output collision on the bus can be prevented with a relatively small scale of circuit.
Claims12
A reset circuit for a flipflop, said flipflop receiving an external clock to generate an output, the reset circuit comprising:
- an internal clock generating circuit for generating an internal clock different from said external clock;
- and
- a clock selecting circuit receiving said external clock and said internal clock for supplying said internal clock to a clock input terminal of said flipflop at a power-on time where the output of said flipflop becomes indefinite, thereby to prevent instability of the output of the flipflop at the power-on time.
A reset circuit for a flipflop, said flipflop receiving an external clock to generate an output, the reset circuit comprising:
- an internal clock generating circuit for generating an internal clock different from said external clock;
- and
- a clock selecting circuit receiving said external clock and said internal clock for supplying said internal clock to a clock input terminal of said flipflop at a power-on time where the output of said flipflop becomes indefinite, thereby to prevent instability of the output of the flipflop at the power-on time,
- wherein said clock selecting circuit includes a power-on-reset circuit for generating a power-on-reset signal having a predetermined active period of time at the power-on time, and a selector circuit for supplying said internal clock generated by said internal clock generating circuit, to said clock input terminal of said flipflop during a period of time in which said power-on-reset signal is active, said selector circuit supplying said external clock to said clock input terminal of said flipflop after said power-on-reset signal is rendered inactive.
Dependencies are inferred from the claim text.