Delay circuit for delaying a high frequency signal and capable of adjusting an effective pulse width

A delay circuit, comprising:

• a first level transition means for receiving an input signal having two different logic levels and varying the pulse width of the same;
• a second level transition means connected with the first level transition means for varying a pulse width of a signal output from the first level transition means;
• a delay unit for delaying an output signal from the second level transition means;
• a duty detection means for generating a duty detection signal from a signal output by the delay unit, the duty detection means having a logic combining circuit for logically combining input signals to the first and second level transition means and the duty detection signal as respective output signals for activating and non-activating the first and second level transition means, each of the first and second level transition means includes:
• an inverting means for inverting a signal input to the inverting means;
• a MOS transistor having a gate electrode for receiving the sign input to the inverting means and its first and second electrodes for receiving an output signal from the inverting means;
• a resistor connected between the first electrode and the second electrode;
• and
• a capacitor connected between the second electrode and a ground.

A delay circuit, comprising:

• a first level transition means for receiving an input signal having two different logic levels and varying a pulse width of the input signal;
• a second level transition means connected with the first level transition mean for varying a pulse width of a signal output from the first level transition means;
• a delay unit for delaying an output signal from the second level transition means;
• a duty detection means for detecting a duty ratio from a signal outputted by the delay unit and outputting a logic signal based on a comparison between the detected duty ratio and a reference duty ratio;
• and
• a logic circuit for outputting signals for activating the first or second level transition means by logically combining signals input to the first and second level transition means and the logic signal from the duty detection means.

A delay circuit, comprising:

• a first level transition means for receiving an input signal having two different logic levels and varying a pulse width of the input signal;
• a second level transition means connected with the first level transition means for varying a pulse width of a signal output from the first level transition means;
• a delay unit for delaying an output signal from the second level transition means;
• a duty detection means for detecting a duty ratio from a signal outputted by the delay unit and outputting a logic signal based on a comparison between the detected duty ratio and a reference duty ratio;
• and
• a logic circuit for outputting signals for activating the first and second level transition means, said logic circuit including:
• a first logic gate for NANDing an input signal of the first level transition means and the logic signal from the duty detection means;
• a first inverter for inverting an output of the first logic gate and outputting it to the first level transition means;
• a second inverter for inverting the logic signal of the duty detection means;
• and
• a second logic gate for NORing an output signal of the first level transition means and an output signal of the second inverter, and outputting a NOR results to the second level transition means.