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US 6,147,535 AGranted
Clock phase generator for controlling operation of a DRAM array
AssigneeMoSys, Inc.
InventorWingyu Leung
Life of this patent
Estimating the term…
Abstract
A structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.
Claims3
A clock phase generator comprising:
- a clock period measuring portion having a delay line including a plurality of delay elements for measuring a clock period of a clock signal, wherein the measuring portion outputs a count corresponding to a number of the delay elements in the delay line which provide a delay equal to approximately one clock period;
- at least one additional delay line including a plurality of delay elements, the additional delay line having a delay equal to a fraction of the delay provided by the delay line in the clock period measuring portion;
- wherein the additional delay line is coupled to receive the clock signal and outputs a signal having a fixed clock phase relationship to the clock signal, wherein the clock phase is equal to the fraction.
Dependencies are inferred from the claim text.