PLL circuit capable of preventing malfunction of FF circuits connected thereto and semiconductor integrated circuit including the PLL circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMasahiro Ueda
Life of this patent
Estimating the term…
Abstract
A PLL circuit including a delay circuit which delays an output of one of inverters constituting a VCO by an amount designated externally via a delay control circuit. An operational circuit carries out logical operation between the output of the delay circuit and an output of the final stage inverter of the inverters, and outputs a second clock signal whose duty differs from that of a first clock signal output from a buffer circuit. The two clock signals are supplied to flip-flop circuits of different circuit blocks so as to prevent malfunction of these flip-flop circuits.
Claims12
A PLL circuit including a voltage controlled oscillator that includes an odd number of stages of inverters, said PLL circuit comprising:
- a first delay circuit connected between two adjacent inverters of said inverters;
- a first delay control circuit for controlling a delay time of said first delay circuit in response to a first delay control circuit external command;
- a buffer circuit connected to a last stage of said inverters for producing a first clock signal with a period at which said PLL circuit locks;
- and
- an operational circuit for carrying out logic operation between a first input and a second input, and for generating a second clock signal, at least one of a duty and a frequency of said second clock signal being different from that of said first clock signal, said first input being at least one signal selected from among an output signal of said first delay circuit and output signals of said inverters, and said second input being a signal output from said inverters, wherein said signal output from said inverters is also input to said buffer circuit.
A semiconductor integrated circuit comprising a PLL circuit, said semiconductor integrated circuit comprising:
- a first circuit block including flip-flop circuits to which first data is supplied;
- a second circuit block including flip-flop circuits to which second data is supplied;
- and
- a PLL circuit including a voltage controlled oscillator that includes an odd number of stages of inverters, wherein said PLL circuit comprises:
- a first delay circuit connected between two adjacent inverters of said inverters;
- a first delay control circuit for controlling a delay time of said first delay circuit in response to a first delay control circuit external command;
- a buffer circuit connected to a last stage of said inverters for producing a first clock signal with a period at which said PLL circuit locks;
- and
- an operational circuit for carrying out logic operation between a first input and a second input, and for generating a second clock signal, at least one of a duty and a frequency of said second clock signal being different from that of said first clock signal, said first input being at least one signal selected from among an output signal of said first delay circuit and output signals of said inverters, and said second input being a signal output from said inverters, wherein said signal output from said inverters is also input to said buffer circuit;
- a first driver circuit connected to the flip-flop circuits in said first circuit block, wherein said first driver circuit provides said flip-flop circuits in said first circuit block with the first clock signal output from said buffer circuit;
- and
- a second driver circuit connected to the flip-flop circuits in said second circuit block, wherein said second driver circuit provides said flip-flop circuits in said second circuit block with the second clock signal output from said operational circuit.
A PLL circuit including a voltage controlled oscillator that includes an odd number of stages of inverters, said PLL circuit comprising:
- a first delay circuit connected between two adjacent inverters of said inverters;
- a first delay control circuit for controlling a delay time of said first delay circuit in response to a first delay control circuit external command;
- a buffer circuit connected to a last stage of said inverters for producing a first clock signal having a period;
- and
- an operational circuit for carrying out logic operation between a first input and a second input, and for generating a second clock signal, at least one of a duty and a frequency of said second clock signal being different from that of said first clock signal, said first input being at least one signal selected from among an output signal of said first delay circuit and output signals of said inverters, and said second input being a signal output from said inverters, wherein said signal output from said inverters is also input to said buffer circuit.
Dependencies are inferred from the claim text.