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US 6,147,531 AGranted
Sampled delay locked loop insensitive to clock duty cycle
AssigneeAnalog Devices, Inc.
InventorsKevin J. McCall, Janos Kovacs
Life of this patent
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Abstract
A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.
Claims9
A sampled delay locked loop insensitive to clock duty cycle comprising:
- an input terminal for receiving an input signal;
- a clock cycle delay circuit for delaying said input signal by at least one clock cycle to produce a delayed input signal;
- a variable delay circuit for delaying the input signal intermediate said input signal and delayed input signal to produce an intermediate input signal;
- an integrator circuit;
- and
- an edge detector circuit responsive to the input signal to drive the integrator circuit to integrate in a first direction, responsive to the intermediate input signal to drive the integrator circuit to integrate in a second direction and responsive to the delayed input signal to end the integration;
- said variable delay circuit being responsive to said integrator circuit to vary the time of occurrence of the intermediate data signal and the reversal of the integration direction for achieving a zero sum integration.
4 more elements
A system for writing data signals to a disk comprising:
- a delay locked loop circuit, said delay locked loop circuit further comprising:
- a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift;
- an input terminal for receiving a data signal;
- a clock cycle delay circuit for delaying said data signal by at least one clock cycle to produce a delayed data signal;
- wherein said variable delay circuit is operative for delaying the data signal intermediate said data signal and delayed data signal to produce an intermediate data signal;
- an integrator circuit;
- and
- an edge detector circuit, responsive to the data signal to drive the integrator circuit to integrate in a first direction, responsive to the intermediate data signal to drive the integrator circuit to integrate in a second, opposite direction and responsive to the delayed data signal to end the integration;
- said variable delay circuit being responsive to said integrator circuit to vary the time of occurrence of the intermediate data signal and the reversal of the integration direction for achieving a zero sum integration.
6 more elements
Dependencies are inferred from the claim text.