US 6,147,530 AGranted

PLL circuit

AssigneeNEC Corporation

InventorHiromichi Nogawa

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Abstract

In a PLL circuit, a phase comparator compares phases between a data signal train and a regenerated clock generated within the PLL circuit based on a clock with which the data signal train is synchronizing, and outputs a phase error signal. A frequency comparator compares frequencies between the data stream signal and the regenerated clock and outputs a frequency error signal. When the frequency difference between the both is large, only the frequency system loop operates to carry out a frequency pull in operation of the regenerated clock. When the frequency difference becomes smaller than a predetermined value, an operation by the phase system loop is added to carry out a phase pull in operation. When the phase difference becomes a predetermined value, the phase is locked. When the frequency difference exceeds the predetermined value again during the phase locked period, the operation of the phase system loop is suspended and only the frequency system loop carries out the frequency pull in operation.

Claims14

Dependent claims

A PLL circuit comprising:

a phase comparator which detects a phase difference between a synchronized data signal and a regenerated clock signal, and operates to output a phase error signal corresponding to the phase difference;
a frequency comparator which detects a frequency difference between the synchronized data signal and the regenerated clock signal, and operates to output a frequency error signal corresponding to the frequency difference, and the operation of the phase comparator is suspended when the frequency difference exceeds a predetermined value;
and
a variable frequency signal generating device that generates and outputs the regenerated clock signal based on the phase error signal and the frequency error signal;
wherein
a frequency pull-in operation is carried out so that the frequency difference is canceled by a loop control using a frequency voltage control signal corresponding to the frequency difference, and in a frequency locked state, wherein the frequency difference is below the predetermined value, the phase comparator cooperates with the frequency comparators and a phase pull-in operation to cancel the phase differences and a phase locking operation at a value below a predetermined value of the phase differences are carried out by a loop control using a sum of a phase voltage control signal corresponding to the phase error signals and the frequency voltage control signal, and wherein
the frequency comparator outputs a frequency lock signal showing that the frequency locked state has been established, and
the phase comparator detects the phase difference in response to the supply of the frequency lock signal thereto,
wherein in the case that the frequency is not locked, the phase voltage control signal is set to a value corresponding to a center voltage of one of either a phase lock range in the phase locking operation, and a phase capture range which is a range of the phase pull-in operation.

6 more elements

A PLL circuit comprising:

a phase comparator which detects a phase difference between a data signal and a phase clock, and outputs a phase error signal corresponding to the phase difference;
a frequency comparator which detects a frequency difference between the data signal and a frequency clock, outputs a frequency error signal corresponding to the frequency difference,;
and
a variable frequency signal generating device which generates the phase clock and the frequency clock based on the phase error signal and the frequency error signal respectively;
wherein and wherein a frequency pull-in operation is carried out so that the frequency difference is canceled by a loop control using a frequency voltage control signal corresponding to the frequency difference, and in a frequency locked state, wherein the frequency difference is below a predetermined value, the phase comparator cooperates with the frequency comparators and a phase pull-in operation to cancel the phase difference, and a phase locking operation at a value below a predetermined value of the phase difference are carried out by controlling a loop using a sum of a phase voltage control signal corresponding to the phase error signal and the frequency voltage control signal, and wherein
the variable frequency signal generating device comprises:
a first charge pump circuit which deposits or removes a charge in response to the supply of the frequency error signal thereto and generates a corresponding frequency charge pump signal which is a direct current voltage;
a frequency low pass filter which smoothes the frequency charge pump signal and generates the frequency voltage control signal;
a second charge pump circuit which deposits or removes a charge in response to the supply of the phase error signal thereto and generates a corresponding phase charge pump signal which is a direct current voltage;
a phase low pass filter which smoothes the phase charge pump signal and outputs the phase voltage control signal;
an adder which adds the frequency voltage control signal to the phase voltage control signal and outputs a sum of both signals;
a first voltage controlled oscillator which oscillates at a frequency corresponding to the frequency voltage control signal and outputs a first oscillation signal;
a divider circuit which divides the first oscillation signal by a predetermined divide ratio and outputs a frequency regenerated clock;
a second voltage controlled oscillator which oscillates at a frequency corresponding to the sum of the phase voltage control signal and the frequency voltage control signal and outputs a second oscillation signal;
and
a divider circuit which divides the second oscillation signal by a predetermined divide ratio and outputs the phase regenerated clock.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/172,770Filed 15 Oct 1998
Priority: JP 9-28217615 Oct 1997
Granted: 14 Nov 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H03L 7/0805
Details of the phase-locked loop: the loop being adapted to provide an additional control signal for use outside the loop
H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…
H03L 7/113
For assuring initial synchronisation or for broadening the capture range: using frequency discriminator