Internal clock generator
AssigneeSamsung Electronics Co., Ltd.
InventorsJung-Bae Lee, Sung-Geun Lee, Jing-Man Han
Life of this patent
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Abstract
An internal clock generator including a switching controller interposed between a digital delay locked loop and an externally generated clock signal. The switching controller reduces current consumptions starting from a next cycle when an external clock and an internal clock are in phase. Further, when the external clock and the internal clock are in phase, driving of the unnecessary elements is suppressed, thereby reducing the current consumption in the internal clock generator.
Claims25
A circuit for synchronizing an internal clock signal with an externally generated clock signal, comprising:
- a digital delay locked loop circuit coupled to receive the externally generated clock signal and output the internal clock signal, said digital delay locked loop circuit having a plurality of unit delay circuits coupled to an associated plurality of phase detection circuits;
- a first switch coupled between the externally generated clock signal and one of the plurality of unit delay circuits;
- a second switch coupled between the externally generated clock signal and the plurality of phase detection circuits;
- and
- a switching controller coupled to said first and second switches for turning on said first and second switches responsive to a switching control signal, said switching controller is coupled to and receives said internal clock signal for turning off said first and second switches when said externally generated clock signal and said internal clock signal are in phase.
A method for synchronizing an externally generated signal with an internal clock signal in a digital delay locked loop circuit having a plurality of unit delay circuits and a plurality of phase detection circuits, the method comprising the steps of:
- interposing a first switch between said externally generated signal and said unit delay circuits, said first switch transmitting said externally generated signal to said unit delay circuits responsive to a switching control signal;
- interposing a second switch between said externally generated signal and said phase detection circuits, said second switch transmitting said externally generated signal to said phase detection circuits responsive to said switching control signal;
- turning on said first and second switches with said switching control signal when said switching control signal undergoes a first transition;
- and
- turning off said first and second switches when said externally generated signal and said internal clock signal are in phase.
An internal clock generator for generating an internal clock synchronized with an external clock, comprising:
- a clock buffer for delaying said external clock for a predetermined time to generate a first clock;
- a main delay circuit having a same time delay value as that of said clock buffer, for generating a second clock being delayed in response to said first clock;
- first and second synchronous delay lines each having a plurality of unit delay circuits coupled in series to delay said first and second clocks for a predetermined unit time;
- a plurality of phase detection circuits for latching signals generated via said unit delay circuits constituting said second synchronous delay line at an interval when a switching control signal activated during a read or write operation transits from a first level to a second level, to generate an activation signal when the latched signal and said first clock are in phase;
- a plurality of first switches coupled to respective output terminals of said unit delay circuits in said first synchronous delay line, for generating output signals of said corresponding unit delay circuits, as said internal clock, in response to the activation signal of said second level;
- a logic controller, coupled in between said clock buffer and said main delay circuit, for providing said first clock to said main delay circuit in response to said switching control signal transiting from the first level to the second level;
- a second switch coupled between an output terminal of said logic controller and an input terminal of said main delay circuit;
- a third switch coupled between an output terminal of said logic controller and input terminals of said phase detection circuits;
- and
- a switching controller for turning on said second and third switches as said switching control signal transits from the first level to the second level so as to provide said first clock to said second synchronous delay line and the input terminals of said phase detection circuits, and for turning off said second and third switches by said internal clock when said first clock and said internal clock are in phase so as to disconnect a path for providing said first clock to said second synchronous delay line and the input terminals of said phase detection circuits.
Dependencies are inferred from the claim text.