Frequency multiplier circuit operable with an external reference clock signal having a frequency in a wide range

A frequency multiplier circuit comprising:

• a voltage controlled delay circuit controlled by a control voltage, including delay cells of plural stages connected in series, an input terminal of a delay cell of a first stage being supplied with a reference clock signal;
• a phase comparator supplied with an output signal of a delay cell of a final stage at a first input terminal and supplied with said reference clock signal at a second input terminal;
• a low-pass filter having an input terminal connected to an output terminal of said phase comparator, and an output terminal connected to an input terminal of a control voltage of said voltage controlled delay circuit;
• a plurality of generation circuits each supplied with a plurality of output signals of said delay cells of plural stages at an input thereof, said generation circuits generating signals of different frequencies to each other, respectively;
• a selection circuit for conducting a selection out of output signals of said plurality of generation circuits according to a frequency selection signal;
• and
• a control circuit for controlling an output timing of said frequency selection signal according to one of the output signals of said delay cells of plural stages.

A frequency multiplier circuit comprising:

• a voltage controlled delay circuit controlled by a control voltage, including delay cells of plural stages connected in series, an input terminal of a delay cell of a first stage being supplied with a reference clock signal;
• a phase comparator supplied with an output signal of a delay cell of a final stage at a first input terminal and supplied with said reference clock signal at a second input terminal;
• a low-pass filter having an input terminal connected to an output terminal of said phase comparator, and an output terminal connected to an input terminal of control voltage of said voltage controlled delay circuit;
• and
• a plurality of generation circuits for generating clock signals provided so as to respectively correspond to latch circuits for latching output signals of a plurality of macro blocks forming a microcomputer, said clock signals controlling operations of said latch circuits,
• wherein when measuring operation speed of said macro blocks, said generation circuit supplies clock signals of different timing to latch circuits for latching the output signals of macro blocks to be measured, according to a plurality of output signals of said delay cells of plural stages.