Power edge detector
AssigneeMicon Design Technology Co., Ltd.
InventorPeter Chang
Life of this patent
Estimating the term…
Abstract
A power edge detector includes a voltage divider, a pull-up circuit, and a cut-in pull-down circuit. The voltage divider receives and divides an input power voltage so as to generate a divided voltage. The pull-up circuit receives the input power voltage and transmits the input power voltage to an output terminal when the input power voltage does not exceed a predetermined threshold. The cut-in pull-down circuit is connected to the voltage divider and the pull-up circuit for pulling down the voltage level of the output terminal in response to the divided voltage when the input power voltage exceeds the predetermined threshold.
Claims17
A power edge detector, comprising:
- a voltage divider receiving and dividing an input power voltage to generate a divided voltage;
- said voltage divider comprising:
- a first PMOS transistor having its source for receiving said input power voltage, and its gate and its drain for outputting said divided voltage;
- a second PMOS transistor having its source for outputting said divided voltage;
- and
- a first NMOS transistor having its gate for receiving a control signal, its drain connected to the drain of said second PMOS transistor, and its source connected to a ground potential;
- a pull-up circuit receiving said input power voltage and transmitting said input power voltage to an output terminal when said input power voltage is less than a predetermined threshold;
- and
- a cut-in pull-down circuit connected to said voltage and said divided pull-up circuit for pulling down a voltage level of said output terminal in response to said divided voltage when said input power voltage exceeds said predetermined threshold.
A power edge detector, comprising:
- a voltage divider receiving and dividing an input power voltage to generate a divided voltage;
- a pull-up circuit receiving said input power voltage and transmitting said input power voltage to an output terminal when said input power voltage is less than a predetermined threshold;
- wherein said pull-up circuit comprises an input/ground/output PMOS transistor having its source coupled to said input power voltage, its gate connected to a ground potential, and its drain connected to said output terminal;
- and
- a cut-in pull-down circuit connected to said voltage divider and said pull-up circuit for pulling down a voltage level of said output terminal in response to said divided voltage when said input power voltage exceeds said predetermined threshold, said voltage divider comprising a receiving/outputting/outputting PMOS transistor having its source for receiving said input power voltage, and its gate and its drain for outputting said divided voltage and an outputting/ground/ground PMOS transistor having its source for outputting said divided voltage, and is gate and its drain coupled to said ground potential.
A power edge detector, comprising:
- a voltage divider receiving and dividing an input power voltage to generate a divided voltage;
- a pull-up circuit receiving said input power voltage and transmitting said input power voltage to an output terminal when said input power voltage is less than a predetermined threshold;
- and
- a cut-in pull-down circuit connected to said voltage divider and said pull-up circuit for pulling down a voltage level of said output terminal in response to said divided voltage when said input power voltage exceeds said predetermined threshold;
- wherein said cut-in pull-down circuit comprises a first NMOS transistor having its drain connected to said output terminal, its gate connected to said divided voltage, and its source connected to a ground potential;
- and
- an input/control/divided PMOS transistor having its source connected to said input power voltage, its gate connected to a control signal, and its drain connected to said divided voltage.
Dependencies are inferred from the claim text.