US 6,147,515 AGranted

Differential receiver

AssigneeSun Microsystems, Inc.

InventorsMichael A. Ang, Alexander D. Taylor, Jonathan E. Starr

Life of this patent

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Abstract

A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Claims35

Dependent claims

A differential receiver comprising

a first pair of transistors, each of the first pair of transistors including a drain, a source and a gate, the source of one of the first pair of transistors being coupled to the drain of another of the first pair of transistors, the drain of the one of the first pair of transistors being coupled to a first node, the gate of the one of the first pair of transistors being coupled to a node enable signal, and the gate of the another of the first pair of transistors being coupled to a reference voltage, the first pair of transistors providing a voltage at the first node indicative of the reference voltage when the node enable signal is active;
a second pair of transistors, each of the second pair of transistors including a drain, a source and a gate, the source of one of the second pair of transistors being coupled to the drain of another of the second pair of transistors, the drain of the one of the second pair of transistors being coupled to a second node, the gate of the one of the second pair of transistors being coupled to the node enable signal, and the gate of the another of the second pair of transistors being coupled to an input signal, the second pair of transistors providing a voltage at the second node indicative of the voltage of the input signal when the node enable signal is active;
and
a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active and the node enable signal is active, the resolving circuit including
a first inverter, the first inverter including first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain, and
a second inverter, the second inverter including first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain,
the drains of the first and second transistors of the first inverter being coupled to the gates of the first and second transistors of the second inverter and to the first node;
and
the drains of the first and second transistors of the second inverter being coupled to the gates of the first and second transistors of the first inverter and to the second node.

6 more elements

A differential receiver comprising:

a first variable resistor having a first resistance value, the first variable resistor being coupled between a first node and a fixed voltage, the first resistance value of the first variable resistor being controlled by a reference voltage, the first variable resistor providing a voltage at the first node indicative of the reference voltage;
a second variable resistor having a second resistance value, the second variable resistor being coupled between a second node and the fixed voltage, the second resistance value of second variable resistor being controlled by an input signal, the second variable resistor providing a voltage at the second node indicative of the input signal;
and
a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active, the resolving circuit including
a first inverter, the first inverter including first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain, and
a second inverter, the second inverter including first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain,
the drains of the first and second transistors of the first inverter being coupled to the gates of the first and second transistors of the second inverter and to the first node;
and
the drains of the first and second transistors of the second inverter being coupled to the gates of the first and second transistors of the first inverter and to the second node.

6 more elements

Dependencies are inferred from the claim text.

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Abstract

A differential receiver comprising

a first pair of transistors, each of the first pair of transistors including a drain, a source and a gate, the source of one of the first pair of transistors being coupled to the drain of another of the first pair of transistors, the drain of the one of the first pair of transistors being coupled to a first node, the gate of the one of the first pair of transistors being coupled to a node enable signal, and the gate of the another of the first pair of transistors being coupled to a reference voltage, the first pair of transistors providing a voltage at the first node indicative of the reference voltage when the node enable signal is active;
a second pair of transistors, each of the second pair of transistors including a drain, a source and a gate, the source of one of the second pair of transistors being coupled to the drain of another of the second pair of transistors, the drain of the one of the second pair of transistors being coupled to a second node, the gate of the one of the second pair of transistors being coupled to the node enable signal, and the gate of the another of the second pair of transistors being coupled to an input signal, the second pair of transistors providing a voltage at the second node indicative of the voltage of the input signal when the node enable signal is active;
and
a resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active and the node enable signal is active, the resolving circuit including
a first inverter, the first inverter including first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain, and
a second inverter, the second inverter including first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain,
the drains of the first and second transistors of the first inverter being coupled to the gates of the first and second transistors of the second inverter and to the first node;
and
the drains of the first and second transistors of the second inverter being coupled to the gates of the first and second transistors of the first inverter and to the second node.

6 more elements